OM5193H Datasheet, PDF (15/56 Pages) NXP Semiconductors – Disk drive spindle and VCM with servo controller

Philips Semiconductors
Disk drive spindle and VCM with
servo controller
Product specification
OM5193H
Table 4 Address of registers
R/W
A2
A1
A0
REG.
DESCRIPTION
0
0
0
0
0 ADC channel and programmable options
1
0
0
0
0 ADC status and value
0
0
0
1
1 commutation, sleep, and VCM switch controls
1
0
0
1
1 commutation state in manual mode
0
0
1
0
2 10-bit DAC
0
0
1
1
3 not used
0
1
0
0
4 not used
0
1
0
1
5 Blank 1 and Watchdog delays
0
1
1
0
6 commutation delay limit (11 bits), internal clock divider factor
0
1
1
1
7 Start-up and Blank 2 delays
8.2 Commutation and sleep mode
Spindle control and sleep mode are controlled by writing or
reading on register#1.
• Register#1 (0, 1 and 2) control the spindle
commutations in manual mode when run/stop, manual
and sleep bits are correctly set. The commutation
sequence is described in Section “Spindle driver” (see
also Table 16 and Fig.12).
• Register#1 (3) is the run/stop bit. After the power is
turned on and POR is HIGH, the motor will not start
spinning until register#1 (3) has been set to logic 1.
The motor stops spinning when this bit is set to logic 0.
• Register#1 (4) is the manual commutation mode bit.
When this bit is set to logic 1 and register#1 (3) set to
logic 1, the commutation logic in the OM5193H will be
disabled so that the spindle will not automatically go to
the next commutation.
When register#1 (3 and 4) are set to logic 1, the
microcontroller is expected to generate the different
commutation states for the motor. The OM5193H will
still provide the coil status which will be available by
reading register#1. The different waveforms are shown
in Section “Spindle driver” (see also Fig.12). Note that
depending on the coil status acquisition moment,
transient states (due to the flyback pulses) can be read.
When register#1 (4) is set to logic 0, the manual mode
is disabled and the OM5193H will automatically
commutate the motor each time a zero crossing is
detected. The time between the zero crossing and the
next commutation is half the time between the two
preceding zero crossings. This is explained in the
detailed description in Section “Commutation control”.
• Register#1 (5) is the spindiv bit. This bit together with
register#6 (11) enables the selection of a divider factor
for both converter clock and spindle clock. Clock
configurations are described in Section “Commutation
control” (see also Table 6).
• Register#1 (6) is the sleep mode bit. When it is set to
logic 0, the OM5193H will enter the low power mode.
Then the commutation control generates (101) output
codes on commutation signals to set spindle and VCM
head into sleep mode. This causes the OM5193H to go
into the brake-after-park mode. The only operating
circuits are the power monitor, the voltage reference
generator, the VCM precharge circuit and the serial
interface. The OM5193H is in sleep mode when POR is
LOW.
When the power is first turned on, the POR signal goes
HIGH after the POR delay. The OM5193H is then
automatically set in sleep mode and thus in low power
consumption mode. The VCM DAC output is in
high-impedance mode, the spindle is in the brake mode
and the VCM is in the precharge mode. Only after POR
is HIGH and register#1 (6) is set to logic 1, OM5193H is
ready to be functional. When register#1 (6) goes HIGH,
the VCM DAC outputs the 2.5 V reference voltage.
• Register#1 (11) is dedicated to brake the spindle motor
without going in ‘brake-after-park’ mode.
The commutation sequence is shifted in order to
efficiently brake the motor. This brake, called reverse
brake, is activated when register#1 (11) bit is set to
logic 1. Note that there is no action on the VCM input
signal when the reverse brake is used. When this bit is
set to logic 0, the spindle motor starts again with normal
spindle commutations.
1998 Nov 02
15