74HC4040 Datasheet, PDF (15/24 Pages) NXP Semiconductors – 12-stage binary ripple counter

Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
Table 10: Dynamic characteristics for type 74HCT4040 …continued
GND = 0 V; t_r = t_f = 6 ns. For test circuit see Figure 9.
Symbol
Parameter
Conditions
t_PHL
propagation delay MR to Qn
V_CC = 4.5 V; C_L = 50 pF;
see Figure 8
t_THL, t_TLH
output transition time
V_CC = 4.5 V; C_L = 50 pF;
see Figure 8
t_W
clock pulse width HIGH or LOW V_CC = 4.5 V; C_L = 50 pF;
see Figure 8
master reset pulse width; HIGH V_CC = 4.5 V; C_L = 50 pF;
see Figure 8
t_rec
recovery time MR to CP
V_CC = 4.5 V; C_L = 50 pF;
see Figure 8
f_max
maximum operating frequency V_CC = 4.5 V; C_L = 50 pF;
see Figure 8
[1] C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑(C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz;
f_o = output frequency in MHz;
∑(C_L × V_CC2 × f_o) = sum of outputs;
C_L = output load capacitance in pF;
V_CC = supply voltage in V.
13. Waveforms
Min Typ Max Unit
-
-
68
ns
-
-
22
ns
24
-
-
ns
24
-
-
ns
15
-
-
ns
20
-
-
MHz
V_I
MR input
V_M
t_W
V_I
CP input
1/f_max
t_rem
V_M
t_PHL
Q0 or Qn
output
t_W
t_PLH
t_TLH
t_PHL
V_M
t_THL
001aad590
Fig 8.
74HC4040: V_M = 50 %; V_I = GND to V_CC.
74HCT4040: V_M = 1.3 V; V_I = GND to 3 V.
Clock (CP) to output (Qn) propagation delays, clock pulse width, output transition
times, maximum clock pulse frequency, master reset (MR) pulse width, master
reset to output (Qn) propagation delays and master reset to clock (CP) removal
time.
74HC_HCT4040_3
Product data sheet
Rev. 03 — 14 September 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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