74HC4040 Datasheet, PDF (13/24 Pages) NXP Semiconductors – 12-stage binary ripple counter

Philips Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
Table 9: Dynamic characteristics for type 74HC4040 …continued
GND = 0 V; t_r = t_f = 6 ns. For test circuit see Figure 9.
Symbol
Parameter
Conditions
T_amb = −40 °C to +125 °C
t_PHL, t_PLH propagation delay CP to Q0
propagation delay Qn to Qn+1
see Figure 8
V_CC = 2.0 V; C_L = 50 pF
V_CC = 4.5 V; C_L = 50 pF
V_CC = 6.0 V; C_L = 50 pF
see Figure 8
t_PHL
t_THL, t_TLH
t_W
propagation delay MR to Qn
output transition time
clock pulse width HIGH or LOW
master reset pulse width; HIGH
V_CC = 2.0 V; C_L = 50 pF
V_CC = 4.5 V; C_L = 50 pF
V_CC = 6.0 V; C_L = 50 pF
see Figure 8
V_CC = 2.0 V; C_L = 50 pF
V_CC = 4.5 V; C_L = 50 pF
V_CC = 6.0 V; C_L = 50 pF
see Figure 8
V_CC = 2.0 V; C_L = 50 pF
V_CC = 4.5 V; C_L = 50 pF
V_CC = 6.0 V; C_L = 50 pF
see Figure 8
V_CC = 2.0 V; C_L = 50 pF
V_CC = 4.5 V; C_L = 50 pF
V_CC = 6.0 V; C_L = 50 pF
see Figure 8
V_CC = 2.0 V; C_L = 50 pF
V_CC = 4.5 V; C_L = 50 pF
V_CC = 6.0 V; C_L = 50 pF
t_rec
recovery time MR to CP
see Figure 8
V_CC = 2.0 V; C_L = 50 pF
V_CC = 4.5 V; C_L = 50 pF
V_CC = 6.0 V; C_L = 50 pF
f_max
maximum operating frequency
see Figure 8
V_CC = 2.0 V; C_L = 50 pF
V_CC = 4.5 V; C_L = 50 pF
V_CC = 6.0 V; C_L = 50 pF
[1] C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑(C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz;
f_o = output frequency in MHz;
∑(C_L × V_CC2 × f_o) = sum of outputs;
C_L = output load capacitance in pF;
V_CC = supply voltage in V.
Min Typ Max Unit
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
120 -
24
-
20
-
120 -
24
-
20
-
75
-
15
-
13
-
4.0 -
20
-
24
-
225 ns
45
ns
38
ns
150 ns
30
ns
26
ns
280 ns
56
ns
48
ns
110 ns
22
ns
19
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
MHz
-
MHz
-
MHz
74HC_HCT4040_3
Product data sheet
Rev. 03 — 14 September 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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