74AUP1G373_15 Datasheet, PDF (15/25 Pages) NXP Semiconductors – Low-power D-type transparent latch; 3-state

NXP Semiconductors
74AUP1G373
Low-power D-type transparent latch; 3-state
V_I
OE input
GND
V_CC
output
LOW-to-OFF
OFF-to-LOW
V_OL
V_OH
output
HIGH-to-OFF
OFF-to-HIGH
GND
V_M
t_PLZ
t_PZL
t_PHZ
V_X
V_Y
V_M
t_PZH
V_M
outputs
enabled
outputs
disabled
outputs
enabled
mna644
Measurement points are given in Table 10.
Logic levels: V_OL and V_OH are typical output voltage levels that occur with the output load.
Fig 10. Turn-on and turn-off times
Table 10. Measurement points
Supply voltage
Input
V_CC
0.8 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
V_M
0.5  V_CC
0.5  V_CC
0.5  V_CC
Output
V_M
0.5  V_CC
0.5  V_CC
0.5  V_CC
V_X
V_OL + 0.1 V
V_OL + 0.15 V
V_OL + 0.3 V
V_Y
V_OH  0.1 V
V_OH  0.15 V
V_OH  0.3 V
74AUP1G373
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 4 July 2012
© NXP B.V. 2012. All rights reserved.
15 of 25