TDA8742 Datasheet, PDF (13/21 Pages) NXP Semiconductors – Satellite sound circuit with noise reduction

Philips Semiconductors
Satellite sound circuit with noise reduction
Product specification
TDA8742; TDA8742H
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Output selector control circuit (see also Table 2) and main channel PLL lock-in select [MCS pin 7 (2)]; pins 15,
17, 26, 13 and 7 (10, 13, 22, 8 and 2) MOS inputs and should not be left open-circuit
V_IL
LOW level input voltage limits
V_IM
MID level input voltage limits
for MCS pin only
0
−
1.8 −
1.2 V
2.8 V
V_IMF
MID level input voltage on
V_P must be 1.8 to 13.2 V 17 19 21 %V_P
MCS pin if MCS pin is floating
V_IH
HIGH level input voltage limits
R_IL
low input resistance MCS pin
to ground
3.5 −
V_P V
12 19 26 kΩ
R_IH
high input resistance MCS pin
to V_P
52 80 108 kΩ
I_IL
LOW level input current
V_IL = 0 V
−
<−1 −
µA
(not MCS pin)
I_IH
HIGH level input current
V_IH = 5 V
−
<1 −
µA
(not MCS pin)
Notes
1. At pin 20 (16) the demodulated 1 kHz signal should be present with a typical level of 158 mV (RMS) (−16 dBV), and
THD of maximum 0.5%; V_P = 8 to 3.2 V; T_amb = −20 to +70 °C.
2. Modulation of main channel is OFF; modulation of secondary channels is ON.
3. The electrolytic capacitors at pins 40 and 42 (36 and 38) are removed and 1500 pF capacitors between pin 40 (36)
and ground and between pin 42 (38) and ground are connected. At pins 40 and 42 (36 and 38) the demodulated
1 kHz signals should be present with typical levels of 9 mV (RMS) and THD of maximum 0.5%; V_P = 8 to 3.2 V;
T_amb = −20 to +70 °C.
4. All PLLs locked; R_S1 = R_S2 = 0.68 kΩ.
5. Modulation of secondary channel being measured and main channel is OFF; modulation of other secondary channel
is ON.
6. Modulation of main channel is ON; modulation of secondary channels is OFF.
7. Measured at pins 38 (34) (left) and 30 (26) (right) and no electrolytic capacitors connected to these pins.
October 1994
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