TDA8742 Datasheet, PDF (11/21 Pages) NXP Semiconductors – Satellite sound circuit with noise reduction

Philips Semiconductors
Satellite sound circuit with noise reduction
Product specification
TDA8742; TDA8742H
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Secondary channels 1 and 2 - HF inputs pins 2, 4, 6, 8, 10, 12, 14 and 16 (1, 3, 5, 7, 9, 11, 40 and 42) and
limiters
V_IN1,IN2(rms)
V_i(rms)
R_i
input sensitivity (RMS value)
input signal level (RMS value)
input resistance
S/N(A) = 40 dB
−
0.8 1.5 mV
−
−
200 mV
260 330 380 Ω
Secondary channels 1 and 2 - PLL FM demodulators (input selector in position 1)
f_CCO1
f_CCO2
∆f_OS1/2
R_{S1, S2}
free running frequency PLL1
free running frequency PLL2
lock range of PLLs
series resistance for optimum
frequency response
adjustment
note 3
−
10.7 −
MHz
−
10.52 −
MHz
10 −
11.5 MHz
0
0.68 2.2 kΩ
V_{CDCL,CDCR(rms)}
PLL output voltage pins 40 and pins to be left open-circuit −
9
−
mV
42 (36 and 38) (RMS value)
∆V_CDCL,CDCR
spread of PLL output voltage
over lock range
−
−
±1 dB
Secondary channels - overall performance of LPF and NR (output selectors in position 1)
R_o
output resistance for 75 µs
de-emphasis pins 36 and 32
(32 and 28)
1.9 2.3 2.6 kΩ
R_i
input resistance of output
amplifiers pins 35 and 33
(31 and 29)
95 150 200 kΩ
V_OL,OR
output voltage level pins 25
and 24 (21 and 20)
note 4
−8 −6 −4 dBV
UBS
unbalance voltage outputs
pins 25 and 24 (21 and 20)
note 4
−1 −
+1 dB
THD
total harmonic distortion
note 4
−
0.1 0.5 %
S/N(A)
signal-to-noise ratio
A-weighted; note 4
72 80 −
dB
R_o
output resistance pins 25 and note 4
92 125 150 Ω
24 (21 and 20)
MUTE_att
mute attenuation
output selector in
position 6; note 4
74 −
−
dB
α_S/S
crosstalk attenuation between note 5
−
74 −
dB
secondary channels
α_M/S
crosstalk attenuation from main note 6
channel to secondary
−
74 −
dB
V_offset(DC)
DC offset voltage on
attack/recovery capacitors
pins 29, 39 (25, 35)
all PLLs locked; ∆f = 0 14 16 20 mV
SVRR
supply voltage ripple rejection V_RR = 100 mV; f_i = 70 Hz −
25 −
dB
October 1994
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