TDA4852 Datasheet, PDF (13/16 Pages) NXP Semiconductors – Horizontal and vertical deflection controller for autosync monitors

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(1) clamp pulses triggered by H-sync
(2) clamp pulses triggered by leading edge of V-trigger pulse
(3) clamp pulses triggered by horizontal oscillator
(4) during V-trigger pulse clamp pulses are generated internally
(5) control voltage of PLL1 is corrected during V-trigger pulse
Fig.8 Pulse diagram for composite sync applications (showing reduced influence of V-sync on H-phase and drive pulses for F/V converters).