80C851 Datasheet, PDF (13/22 Pages) NXP Semiconductors – CMOS single-chip 8-bit microcontroller with on-chip EEPROM

Philips Semiconductors
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
Product specification
80C851/83C851
AC ELECTRICAL CHARACTERISTICS^{1, 2}
24 MHz Version
SYMBOL FIGURE
PARAMETER
1/t_CLCL
4
t_LHLL
4
t_AVLL
4
t_LLAX
4
t_LLIV
4
t_LLPL
4
t_PLPH
4
t_PLIV
4
t_PXIX
4
t_PXIZ
4
t_AVIV
4
t_PLAZ
4
Data Memory
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
t_RLRH
5
t_WLWH
5
t_RLDV
5
t_RHDX
5
t_RHDZ
5
t_LLDV
5
t_AVDV
5
t_LLWL
5, 6
t_AVWL
5, 6
t_QVWH
6
t_QVWX
6
t_WHQX
6
t_RLAZ
5
t_WHLH
5, 6
External Clock
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to RD or WR low
Data setup time before WR
Data valid to WR transition
Data hold after WR
RD low to address float
RD or WR high to ALE high
t_CHCX
8
High time
t_CLCX
8
Low time
t_CLCH
8
Rise time
t_CHCL
8
Fall time
Erase/write timer constant³
t_E/W
t_E
t_W
t_S
NE/W
Erase/write cycle time
Erase time
Write time
Data retention time⁴
Erase/write cycles⁵
24MHz CLOCK
MIN
MAX
43
17
17
102
17
80
65
0
17
128
10
150
150
118
0
55
183
210
75
175
92
162
12
17
0
17
67
17
17
5
5
4
20
2
10
2
10
10
10,000
VARIABLE CLOCK
MIN
MAX
3.5
24
2t_CLCL–40
t_CLCL–25
t_CLCL–25
t_CLCL–25
3t_CLCL–45
0
4t_CLCL–65
3t_CLCL–60
t_CLCL–25
5t_CLCL–80
10
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6t_CLCL–100
ns
6t_CLCL–100
ns
5t_CLCL–90
ns
0
ns
2t_CLCL–28
ns
8t_CLCL–150
ns
9t_CLCL–165
ns
3t_CLCL–50
3t_CLCL+50
ns
4t_CLCL–75
ns
7t_CLCL–130
ns
t_CLCL–30
ns
t_CLCL–25
ns
0
ns
t_CLCL–25
t_CLCL+25
ns
17
ns
17
ns
20
ns
20
ns
4
2
2
10
10,000
20
ms
10
ms
10
ms
years
cycles
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. The power-off fall-time of V_DD must be less than 1ms to prevent an overwrite pulse from being generated in the EEPROM which can cause
spurious parasitic writing to EEPROM cells. If the V_DD power-off full-time is greater than 1ms, a power-off reset signal should be generated
to prevent this condition from occurring.
4. Test condition: T_amb = +55°C.
5. Number of erase/write cycles for each EEPROM byte.
1998 Jul 03
13