SA1630 Datasheet, PDF (12/22 Pages) NXP Semiconductors – IF quadrature transceiver

Philips Semiconductors
IF quadrature transceiver
Product specification
SA1630
STROBE pin should be low during power up to guarantee a proper
reset. These default states are shown in Table 2.
Reference Divider
The reference divider can be programmed to four different division
ratios (:8, :11, :22, :44), see registers r0, r1; default setting: divide by
22.
Main Divider
The external VCO signal, applied to the LO_IN and LO_INX inputs, is
divided by two and then fed to the main divider (:N). The main
divider is a programmable 9 bit divider, the minimum division ratio is
divide by 64. The division ratio is binary coded and set in the
registers n0 to n8. The default setting is a divide by 352.
At the completion of a main divider cycle, a main divider output is
generated which will drive the phase detector.
Phase Detector
The phase detector is a D-type flip-flop phase and frequency
detector shown in Figure 5. The flip-flops are set by the negative
edges of the output signals of the dividers. The rising edge of the
signal L will reset the flip-flops after both flip-flops have been set.
Around zero phase error this has the effect of delaying the reset for
1 reference input cycle. This avoids non-linearity or deadband
around zero phase error. The flip-flops drive on-chip charge pumps.
A source current from the charge pump acts to increase the VCO
frequency; a sink current acts to decrease the VCO frequency.
Current Setting
The charge pump current is defined by the current set between the
pin I_REF and V_EECP. The current value to be set there is 31.2µA.
This current can be set by an external resistor to be connected
between the pin I_REF and V_EECP. The typical value R_EXT (current
setting resistor) can be calculated with the formula
R_EXT
+
V_CCCP–1.6V
31.2mA
(44.87K
for
3V)
The current can be set to zero by connecting the pin I_REF to V_CCCP.
Charge Pumps
The charge pumps at pin CP are driven by the phase detector and
the current value is determined by the binary value of the charge
pumps register CN = c2, c1, c0, default .4mA. The active charge
pump current is typically:
|I_CP| + (c0 ) 2c1 ) 4c2) @ 29mA ) 200mA
Lock Detect
The output LOCK is H when the phase detector indicates a lock
condition. This condition is defined as a phase difference of less
than ±1 cycle on the reference input CLK_IN, CLK_INX.
Test Modes (Synthesizer, Transmit Mixer)
The LOCK output is selectable as a test output. Bits x0, x1 control
the selection, the default setting is normal lock output as described
in the Lock detect section. The selection of a Bit x0, x1 combination
has a twofold effect: First it routes a divider output signal to the
LOCK pin, second it disables mixer stages in the transmit path.
Setting x0,1 = 11 disables both transmit path mixers. This mode can
be used to prevent the transmitter from producing an IF output
signal even if the transmit part is powered on. This can be used to
simplify the control timing while commanding the transmit and
receive simultaneously without the transmit part causing
interference.
Table 1. Test Modes
x0 x1
Synthesizer Signal
at LOCK Pin
00
normal lock detect
10
CLK_IN divided by reference
divider ratio
0 1 LO_IN ÷ 2 * (main divider ratio)
1
1
main divider output, that goes to
the phase detector
Transmit Mixer
Q-mixer I-mixer
on
on
off
on
on
off
off
off
1998 Jul 21
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