SA1630 Datasheet, PDF (11/22 Pages) NXP Semiconductors – IF quadrature transceiver

Philips Semiconductors
IF quadrature transceiver
Product specification
SA1630
CURRENT
I₂
I₁
V₁
VOLTAGE
V₂
I₂
I₁
SR00526
Figure 3. Relative Output Current Variation
APPLICATION DESCRIPTION
General
The 1630 performs the IF modulator and demodulator functionality
for high–speed wireless data transceivers. The design is optimized
for IEEE 802.11 wireless LAN using 11 chips/symbol Direct
Sequence Spread Spectrum.
Transmitter
The IF quadrature transmitter baseband modulator input is driven
differentially by the D/A converters in the DSP chip. The baseband
signals are DC coupled for fast turn–on and turn–off and for
constant carrier testing. The typical common–mode input voltage is
VCC/2.
The open collector outputs of the mixers are biased by two
inductors, which are part of an LC tank. The LC tank matches the
output impedance of the mixers to the input impedance of the
upconverter chip (or any filter in between) and suppresses IF
harmonics.
An optional 2.5V reference is available during mode (3) and (5), the
transmit mode with Rx in standby. This reference can be enabled or
disabled via the 3 wire bus (in this mode). This voltage is provided
for use by an external current DAC if needed.
Receiver
The receiver part of the SA1630 consists of an IF Variable gain
amplifier, a quadrature demodulator and a pair of baseband
amplifiers. The IF amplifier has its gain controlled by the DSP chip.
This ensures linear operation of the receiver chain over a wide
dynamic range of input signals. Linear operation is essential for
resolving echo’s due to multipath reception.
The digital controlled AGC is meant for fast level training for the
receiver.
The high gain receiver, which is distributed between the IF and
baseband part facilitates interfacing with the RF front–end chip,
which normally have moderate gains (up to 20 dB), and SAW IF
filters, which mostly have considerable loss (up to 8 dB) without
external amplifiers.
The baseband amplifiers have a high drive capability (1 Vpp into
1kΩ, 15 pF for VCC = 3V) that facilitates direct interfacing to the A/D
converter without active external elements.
The baseband amplifiers can interface directly to the Track/Hold
switch/capacitor combination with capacitance values up to 15 pF.
When sampled at 22MHz the output can settle to within 1/4 LSB
when swinging 1V p–p.
The chip has a unique mode in which the Rx is on standby while the
Tx is ON. In this mode the Rx Baseband circuits are idling at
reduced currents and all Rx I/O outputs retain their DC bias
unchanged from their values when the Rx was fully ON. This mode
is very essential if ac coupling through a large capacitor, such as,
10nF is used. From this mode the chip can quickly be switched to
the Rx ON mode (Tx OFF) without worrying about
charging/discharging the large AC coupling capacitor.
The VGA can be programmed in 2 ways: 1) Directly programming
external control pins. 2) programming over the serial 3–wire bus.
The former method can switch gain in less than 200 ns.
The Rx baseband section also incorporates simple low pass active
filters of the Sallen key type. The Rx bandwidth is mainly set by
these filters. The function of these filters is twofold: 1) attenuate high
frequency signals from the Rx mixers. 2) act as anti–aliasing filters
for any A to D converters following this chip.
IF synthesizer
The SA1630 has an integrated synthesizer that uses an external
VCO operating on twice the IF frequency. It is internally divided by 2
for obtaining quadrature signals. The divided VCO signal is not
externally available. This minimizes the LO feedthrough to the IF
input port and hence minimizes output dc glitches when the IF gain
is switched.
The PLL reference clock is derived from the 22 MHz DSP clock. The
available divider ratios facilitate both 1 and 2 MHz phase
comparison frequency from a 22 MHz and an optional 44 MHz clock
respectively. In essence the reference divider will have
programmable dividers ratios of 8, 11, 22 and 44.
The VCO shall be fed from a stabilized supply. Such a stabilized
supply is necessary in order to prevent oscillator jitters due to Rx/Tx
switching. The effect of oscillator jitters is further minimized when
using a high PLL loop bandwidth, which on its turn requires a high
phase comparison frequency (1 MHz, preferably 2 MHz).
If the IF Synthesizer is not used, the CLK_IN pins should be
terminated to ac ground.
Serial Programming Input
The serial input is a 3–wire input (CLOCK, STROBE, DATA) to
program the counter ratios, charge pump current, status– and
DC–offset register, mode select and test register. The programming
data is structured into two 21–bit words; each word includes 4 chip
address bits and 1 subaddress bit. Figure 2 shows the timing
diagram of the serial input. When the STROBE = L, the clock driver
is enabled and on the positive edges of the CLOCK the signal on
DATA input is clocked into a shift register. When the STROBE = H,
the clock is disabled and the data in the shift register remains stable.
Depending on the value of the subaddress bit the data is latched
into different working registers. Table 3 shows the contents of each
word.
Default States
Upon power up (V_CCDIG is applied) a reset signal is generated,
which sets all registers to a default state. The logic level at the
1998 Jul 21
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