74HC190 Datasheet, PDF (12/13 Pages) NXP Semiconductors – Presettable synchronous BCD decade up/down counter

Philips Semiconductors
Presettable synchronous BCD decade
up/down counter
AC WAVEFORMS
Product specification
74HC/HCT190
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT : V_M = 1.3 V; V_I = GND to 3 V.
Fig.10 Waveforms showing the clock (CP) to
output (Q_n) propagation delays, the clock
pulse width and the maximum clock pulse
frequency.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT : V_M = 1.3 V; V_I = GND to 3 V.
Fig.11 Waveforms showing the clock and count
enable inputs (CP, CE) to ripple clock
output (RC) propagation delays.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT : V_M = 1.3 V; V_I = GND to 3 V.
Fig.12 Waveforms showing the input (D_n) to output
(Q_n) propagation delays.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT : V_M = 1.3 V; V_I = GND to 3 V.
Fig.13 Waveforms showing the input (PL) to output
(Q_n) propagation delays.
(1) HC :
V_M = 50%;
V_I = GND to
V_CC.
HCT :
V_M = 1.3 V;
V_I = GND to
3 V.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT : V_M = 1.3 V; V_I = GND to 3 V.
Fig.14 Waveforms showing the up/down count
input (U/D) to terminal count and ripple
clock output (TC, RC) propagation delays.
Fig.15 Waveforms showing the parallel load input
(PL) pulse width, removal time to clock (CP)
and the output (Q_n) transition times.
December 1990
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