74HC161 Datasheet, PDF (12/12 Pages) NXP Semiconductors – Presettable synchronous 4-bit binary counter; asynchronous reset

Philips Semiconductors
Presettable synchronous 4-bit binary
counter; asynchronous reset
Product specification
74HC/HCT161
The shaded areas indicate when the input is permitted to change
for predictable output performance.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.11 Waveforms showing the set-up and hold times for the input (D_n) and parallel enable input PE.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.12 Waveforms showing the CEP and CET set-up and hold times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
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