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74AUP1G3208 Datasheet, PDF (12/19 Pages) NXP Semiconductors – Low-power 3-input OR-AND gate
Philips Semiconductors
74AUP1G3208
Low-power 3-input OR-AND gate
Table 11: Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10
Symbol Parameter
Conditions
−40 °C to +85 °C
Min
Max
CL = 15 pF
tPHL, tPLH
HIGH-to-LOW and
LOW-to-HIGH
propagation delay
A, B or C to Y
see Figure 9
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2.8
14.6
2.4
9.1
2.1
7.4
VCC = 2.3 V to 2.7 V
1.9
5.5
CL = 30 pF
VCC = 3.0 V to 3.6 V
1.7
4.8
tPHL, tPLH
HIGH-to-LOW and
LOW-to-HIGH
propagation delay
A, B or C to Y
see Figure 9
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
3.7
19.7
3.2
12.1
2.9
9.7
VCC = 2.3 V to 2.7 V
2.6
7.1
VCC = 3.0 V to 3.6 V
2.4
6.4
13. Waveforms
−40 °C to +125 °C Unit
Min
Max
2.8
14.9 ns
2.4
9.5 ns
2.1
7.8 ns
1.9
5.9 ns
1.7
5.0 ns
3.7
20.1 ns
3.2
12.7 ns
2.9
10.3 ns
2.6
7.5 ns
2.4
6.7 ns
VI
A, B, C input
VM
VM
GND
VOH
t PHL
t PLH
Y output
VM
VM
VOL
VOH
t PLH
t PHL
Y output
VM
VM
VOL
001aab593
Fig 9.
Measurement points are given in Table 12.
VOL and VOH are typical output voltage drop that occur with the output load.
Input A, B and C to output Y propagation delay times.
Table 12: Measurement points
Supply voltage
Output
VCC
0.8 V to 3.6 V
VM
0.5 × VCC
Input
VM
0.5 × VCC
74AUP1G3208_1
Preliminary data sheet
Rev. 01.00 — 17 January 2006
VI
tr = tf
VCC
≤ 3.0 ns
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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