ADC1112D125 Datasheet, PDF (11/41 Pages) NXP Semiconductors – Dual 11-bit ADC; CMOS or LVDS DDR digital outputs

NXP Semiconductors
ADC1112D125
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
10.2 Clock and digital output timing
Table 8. Clock and digital output timing characteristics^[1]
Symbol
Parameter
Conditions
Clock timing input: pins CLKP and CLKM
f_clk
t_lat(data)
clock frequency
data latency time
Min
Typ
Max
100
-
125
-
14
-
δ_clk
clock duty cycle
DCS_EN = 1
DCS_EN = 0
30
50
70
45
50
55
t_d(s)
sampling delay time
t_wake
wake-up time
CMOS mode timing: pins DA10 to DA0, DB10 to DB0 and DAV
-
0.8
-
-
76
-
t_PD
propagation delay
DATA
DAV
-
3.9
-
-
4.2
-
t_su
set-up time
t_h
hold time
t_r
rise time
DATA
DAV
-
5.7
-
-
1.4
-
[2] _0.5
-
2.4
0.5
-
2.4
t_f
fall time
DATA
[2] _0.5
-
2.4
LVDS DDR mode timing: pins DA9_DA10_P to LOW_DA0_P, DA9_DA10 M to LOW_DA0_M,
DB9_DB10_P to LOW_DB0_P, DB9_DB10_M to LOW_DB0_M, DAVP and DAVM
t_PD
propagation delay
DATA
DAV
-
3.9
-
-
4.2
-
t_su
set-up time
t_h
hold time
t_r
rise time
DATA
DAV
-
-
[3] ₅₀
50
1.4
-
2.0
-
100
200
100
200
t_f
fall time
DATA
DAV
[3] ₅₀
50
100
200
100
200
Unit
MHz
clock
cycles
%
%
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
[1] Typical values measured at V_DDA = 3 V, V_DDO = 1.8 V, T_amb = 25 °C; minimum and maximum values are across the full temperature
range T_amb = −40 °C to +85 °C at V_DDA = 3 V, V_DDO = 1.8 V; V_INAP − V_INAM = −1 dBFS; V_INBP − V_INBM = −1 dBFS; unless otherwise
specified.
[2] Measured between 20 % to 80 % of V_DDO.
[3] Rise time measured from −50 mV to +50 mV; fall time measured from +50 mV to −50 mV.
ADC1112D125
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 3 March 2011
© NXP B.V. 2011. All rights reserved.
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