TDA6502 Datasheet, PDF (10/44 Pages) NXP Semiconductors – 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners

Philips Semiconductors
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
Preliminary specification
TDA6502; TDA6502A;
TDA6503; TDA6503A
Table 5 Description of the bits used in Tables 3 and 4
BIT
DESCRIPTION
MA1 and MA0
programmable address bits (see Table 6)
R/W
N14 to N0
logic 0 for write mode
programmable divider bits: N = N14 × 2¹⁴ + N13 × 2¹³ + ... + N1 × 2¹ + N0
CP
charge pump current control bit:
logic 0: charge pump current is 60 µA
logic 1: charge pump current is 280 µA (default)
T2, T1 and T0
test bits (see Table 7)
RSA and RSB
reference divider ratio select bits (see Table 8)
OS
tuning amplifier control bit:
logic 0: tuning voltage is ‘on’ (during normal operating)
logic 1: tuning voltage is ‘off’; high-impedance output of pin VT (default)
PVHFL, PVHFH, PUHF and FMST PMOS ports control bits:
logic 0: corresponding buffer is ‘off’ (default)
logic 1: corresponding buffer is ‘on’
X
don’t care
Table 6 Address selection bits (I²C-bus mode)
MA1
0
0
1
1
MA0
0
1
0
1
VOLTAGE APPLIED TO PIN CE/AS
0 V to 0.1V_CC
0.2V_CC to 0.3V_CC or open-circuit
0.4V_CC to 0.6V_CC
0.9V_CC to 1.0V_CC
Table 7 Test mode bits
T2
T1
T0
TEST MODE
0
0
0
normal mode
0
0
1
normal mode (note 1)
0
1
X
charge pump is off
1
1
0
charge pump is sinking current
1
1
1
charge pump is sourcing current
1
0
0
f_REF is available on pin LOCK/ADC (note 2)
1
0
1
1_{⁄2fDIV is available on pin LOCK/ADC (note 2)}
Notes
1. This is the default mode at Power-on reset.
2. The ADC input cannot be used when these test modes are active; see Section 8.2.3 for more information.
2000 Mar 16
10