TDA5147K Datasheet, PDF (10/32 Pages) NXP Semiconductors – 12 V Voice Coil Motor VCM driver and spindle motor drive combination chip

Philips Semiconductors
12 V Voice Coil Motor (VCM) driver and
spindle motor drive combination chip
Product specification
TDA5147K
PARK ENABLE
A 3-state-level mode line (V_PCNTL) has been included that
will:
1. Enable VCM drivers; V_CCA1 (normal).
2. Disable VCM drivers; 0.5V_CCA1.
3. PARK (soft retract the actuator); 0 V.
Enable VCM drivers
When the enable signal is HIGH, the VCM drivers are
controlled by the two PWM inputs. The two digital signals
convert the duty factor to a voltage level at V_FLTOUT. At a
100% duty factor the V_FLTINP voltage is approximately 1 V
above V_ref(o). At a 0% duty factor the V_FLTINP voltage is
approximately −1 V below V_ref(o). At a 50% duty factor, the
voltage level is equal to V_ref(o) (typical 4 V). The V_FLTINP
voltage is amplified, filtered and output at V_FLTOUT. The
voltage at V_FLTOUT varies between ±2 V about V_ref(o). The
V_FLTOUT voltage, in conjunction with the sense resistor
amplifier, drives the two VCM drivers as illustrated in Fig.8.
The transconductance equation that governs the voltage
from V_FLTINP to I_coil is:
G_m = _V-----F---_L---_T---_I-_N---I-_P-^c---^o_–---ⁱ-^l-V----_r--_e---_f--₍--_o---₎-= -₍---V----_F---_L---_T---_O----_U--I--_Tc--^o--_–-ⁱ-^l--V----_r--_e---_f--₍--_o---₎---₎-
= 2 × _{g----a-1---i--n--} × ^RR-----21-- × _R--1---s- Amps per Volt
In a typical application:
V-----_F^---_L^---_T^---_I^-_N^---I-_P^-c---o–^---i-l-V----_r^--_e^---_f^--₍^--_o^---₎^{-= 24-- × -61---.-06-----k-k--}Ω^{-Ω--- ×} 0----.-13----3--^{= 1 Amp per Volt}
The transconductance is variable by selecting external
resistors R2/R1 and sense resistors R_s
Disable VCM drivers
With the PARK enable signal at 0.5V the VCM drivers are
disabled while the rest of the circuits remain enabled.
A sleep mode is initiated when the spindle and VCM are
disabled (this places the TDA5147K in its lowest power
setting).
ACTUATOR PARK
Retracting the actuator can be accomplished by driving
V_PCNTL LOW in conjunction with either the spindle is
turning or a brake voltage has been applied. An adjustable
retract voltage of 1.2 V (max.) is applied between the V_CMN
and V_CMP outputs. The retract circuit obtains its retract
current from the spindle SDRVU phase. If the SDRVU
phase is zero there will be no retract voltage.
The retract voltage is determined by two external resistors.
One end is tied to V_CMN and the other to ground. The
common point is tied to pin 22 (RET_ADJ); see Fig.1 for
additional information.
The calculation of V_RETRACT is as follows:
V_RETRACT
=
0.65
×


1-----+_{R-----1R-----2--}
+
5----0-R----k2---Ω^---


Where 0.65 is V_BE at 25 °C ∆V_BE/∆T = −2 mV/°C; 50 kΩ
can vary by ±30%
It should be noted that R2 has to be less than 10 kΩ.
Power-on reset
The power-on reset circuit monitors the voltage levels of
both the +5 V and the +12 V supply voltages as shown
in Fig.6. The POR (active LOW) logic line is set HIGH
following a supply voltage rise above a specified voltage
threshold plus a hysteresis, and delayed by a time, t_C that
is controlled by an external capacitor. This POR signal
should remain HIGH until either the +5 or +12 V supplies
drop below the voltage threshold, at which point the POR
line should be asserted LOW.
The t_C timing is set by the following equation:
t_C = ^C------×---I--V----^t--^h-
Where V_th = 2.5 V and I is 12 µA (typ.).
A negative going pulse width of 5 µs on either the
+5 or +12 V rail will provide a full output pulse. If another
trigger pulse occurs before the output is completed a new
output pulse will be originated. This implies the power-on
reset circuit is a retriggerable one-shot with a maximum
trigger pulse of 5 µs (see Fig.7).
1996 Jul 26
10