PIP3102-R Datasheet, PDF (10/13 Pages) NXP Semiconductors – LOGIC LEVEL TOPFET

Philips Semiconductors
Logic level TOPFET
Product Specification
PIP3102-R
VDS
0
ID
0
VIS
0
V(CL)DSR
VDD
L
+ ^VDD
RF
RI = RIS
+ ^VPS
P
F
P
I
VDS
D
TOPFET
D.U.T.
S
-
R 01
shunt
-ID/100
Fig.26. Clamping energy test circuit, R_IS = 100 Ω.
E_DSM = 0.5 ⋅ L I_D² ⋅ V_(CL)DSR/(V_(CL)DSR − V_DD)
E_DSM / J
1.2
1.0
25^OC
0.8
0.6
150^OC
0.4
0.2
0
0.1
1
L / mH
10
100
Fig.27. Typical non-repetitive clamping energy.
E_DSM = f(L); conditions: V_IS = 0 V
4 ^{ID / A}
3
2
1
0
50
60
70
V_DS / V
Fig.28. Typical clamping characteristic, 25˚C.
I_D = f(V_DS); conditions: V_IS = 0 V; t_p ≤ 300 µs
VII
RI
RIS
D
TOPFET
P
VIS
F
P
I
S
Fig.29. Test circuit for resistive load switching times.
V_IS = 5 V
V_IS & V_DS / V
16
14
V_DS
12
10
8
V_IS
6
4
2
0
0 5 10 15 20 25 30 35 40 45 50
Time / µs
Fig.30. Typical switching waveforms, resistive load.
R_L = 10 Ω; adjust V_DD to obtain I_D = 1.5 A; T_j = 25˚C
65 ^{VDSS / V}
I_D =
4A
10mA
60
-50
0
50
100
150
T_j / ^OC
Fig.31. Overvoltage clamping characteristic.
V_DS = f(T_j); conditions: V_IS = 0 V; t_p ≤ 300 µs
October 2002
10
Rev 1.000