74HC166 Datasheet, PDF (10/10 Pages) NXP Semiconductors – 8-bit parallel-in/serial-out shift register

Philips Semiconductors
8-bit parallel-in/serial-out shift register
Product specification
74HC/HCT166
The number of clock pulses required between the t_PLH and t_PHL
measurements can be determined from the function table.
CE may change only from HIGH-to-LOW while CP is LOW.
The shaded areas indicate when the input is permitted to change for
predictable output performance.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3V; V_I = GND to 3V.
Fig.9 Waveforms showing the set-up and hold times from the serial data input (D_s), the data inputs (D_n), the
clock enable input (LOW CE), the clock enable input CE and the parallel enable input to the clock (CP).
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
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