SSTU32866 Datasheet, PDF (1/29 Pages) NXP Semiconductors – 1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity for DDR2 RDIMM applications

SSTU32866
1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer
with parity for DDR2 RDIMM applications
Rev. 02 — 11 November 2004
Product data sheet
1. General description
The SSTU32866 is a 1.8 V configurable register specifically designed for use on DDR2
memory modules requiring a parity checking function. It is defined in accordance with the
JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity
checking function in a compatible pinout. The JEDEC standard for SSTU32866 is pending
publication. The register is configurable (using configuration pins C0 and C1) to two
topologies: 25-bit 1:1 or 14-bit 1:2, and in the latter configuration can be designated as
Register A or Register B on the DIMM.
The SSTU32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN)
input, compares it with the data received on the DIMM-independent D-inputs and
indicates whether a parity error has occurred on its open-drain QERR pin (active-LOW).
The convention is even parity, that is, valid parity is defined as an even number of ones
across the DIMM-independent data inputs combined with the parity input bit.
The SSTU32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA package
(13.5 mm by 5.5 mm).
2. Features
s Configurable register supporting DDR2 Registered DIMM applications
s Configurable to 25-bit 1:1 mode or 14-bit 1:2 mode
s Controlled output impedance drivers enable optimal signal integrity and speed
s Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation
delay; 2.0 ns max. mass-switching)
s Supports up to 450 MHz clock frequency of operation
s Optimized pinout for high-density DDR2 module design
s Chip-selects minimize power consumption by gating data outputs from changing state
s Supports SSTL_18 data inputs
s Checks parity on the DIMM-independent data inputs
s Partial parity output and input allows cascading of two SSTU32866s for correct parity
error processing
s Differential clock (CK and CK) inputs
s Supports LVCMOS switching levels on the control and RESET inputs
s Single 1.8 V supply operation
s Available in 96-ball, 13.5 × 5.5 mm, 0.8 mm ball pitch LFBGA package