PSMN010-55D Datasheet, PDF (1/9 Pages) NXP Semiconductors – N-channel logic level TrenchMOSÔ transistor

Philips Semiconductors
Product specification
N-channel logic level TrenchMOS™ transistor
PSMN010-55D
FEATURES
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• Logic level compatible
SYMBOL
d
g
s
QUICK REFERENCE DATA
V_DSS = 55 V
I_D = 75 A
R_DS(ON) ≤ 10.5 mΩ (V_GS = 10 V)
R_DS(ON) ≤ 12 mΩ (V_GS = 5 V)
GENERAL DESCRIPTION
SiliconMAX products use the latest
Philips Trench technology to
achieve the lowest possible
on-state resistance in each
package at each voltage rating.
Applications:-
• d.c. to d.c. converters
• switched mode power supplies
The PSMN010-55D is supplied in
the SOT428 (Dpak) surface
mounting package.
PINNING
PIN
DESCRIPTION
1 gate
2 drain¹
3 source
tab drain
SOT428 (DPAK)
tab
2
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DSS
V_DGR
V_GS
V_GSM
I_D
I_DM
P_D
T_j, T_stg
Drain-source voltage
Drain-gate voltage
Continuous gate-source
voltage
Peak pulsed gate-source
voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
T_j = 25 ˚C to 175˚C
T_j = 25 ˚C to 175˚C; R_GS = 20 kΩ
T_j ≤ 150 ˚C
T_mb = 25 ˚C; V_GS = 5 V
T_mb = 100 ˚C; V_GS = 5 V
T_mb = 25 ˚C
T_mb = 25 ˚C
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
55
55
± 15
± 20
75²
57
240
125
175
UNIT
V
V
V
V
A
A
A
W
˚C
1 It is not possible to make connection to pin 2 of the SOT428 package.
2 Continuous current rating limited by package.
October 1999
1
Rev 1.200