PHW50NQ15T Datasheet, PDF (1/7 Pages) NXP Semiconductors – N-channel TrenchMOS transistor

Philips Semiconductors
N-channel TrenchMOS™ transistor
Product specification
PHW50NQ15T
FEATURES
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• Low thermal resistance
SYMBOL
d
g
s
QUICK REFERENCE DATA
V_DSS = 150 V
I_D = 50 A
R_DS(ON) ≤ 35 mΩ
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a
plastic envelope using ’trench’
technology.
Applications:-
• d.c. to d.c. converters
• switched mode power supplies
The PHW50NQ15T is supplied in
the SOT429 (TO247) conventional
leaded package.
PINNING
PIN
DESCRIPTION
1 gate
2 drain
3 source
tab drain
SOT429 (TO247)
1 23
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DSS
V_DGR
V_GS
I_D
I_DM
P_D
T_j, T_stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
T_j = 25 ˚C to 175˚C
T_j = 25 ˚C to 175˚C; R_GS = 20 kΩ
T_mb = 25 ˚C
T_mb = 100 ˚C
T_mb = 25 ˚C
T_mb = 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
150
150
± 20
50
36
200
250
175
UNIT
V
V
V
A
A
A
W
˚C
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
E_AS
Non-repetitive avalanche Unclamped inductive load, I_AS = 47 A;
energy
t_p = 100 µs; T_j prior to avalanche = 25˚C;
V_DD ≤ 50 V; R_GS = 50 Ω; V_GS = 10 V; refer
to fig;15
I_AS
Non-repetitive avalanche
current
MIN.
-
MAX.
460
UNIT
mJ
-
50
A
August 1999
1
Rev 1.000