BUK9775-55 Datasheet, PDF (1/8 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
BUK9775-55
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic full-pack envelope using
’trench’ technology. The device
features very low on-state resistance
and has integral zener diodes giving
ESD protection up to 2kV. It is
intended for use in automotive and
general purpose switching
applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
V_DS
I_D
P_tot
T_j
R_DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
V_GS = 5 V
MAX.
55
11.7
19
150
75
PINNING - SOT186A
PIN
DESCRIPTION
1 gate
2 drain
3 source
case isolated
PIN CONFIGURATION
case
12 3
SYMBOL
d
g
s
UNIT
V
A
W
˚C
mΩ
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DS
V_DGR
±V_GS
I_D
I_D
I_DM
P_tot
T_stg, T_j
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
-
R_GS = 20 kΩ
-
T_mb = 25 ˚C
T_mb = 100 ˚C
T_mb = 25 ˚C
T_mb = 25 ˚C
-
ESD LIMITING VALUE
SYMBOL
V_C
PARAMETER
Electrostatic discharge capacitor
voltage, all pins
CONDITIONS
Human body model
(100 pF, 1.5 kΩ)
THERMAL RESISTANCES
SYMBOL
R_{th j-mb}
R_{th j-a}
PARAMETER
Thermal resistance junction to
heatsink
Thermal resistance junction to
ambient
CONDITIONS
with heatsink compound
in free air
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
10
11.7
7.4
47
19
150
UNIT
V
V
V
A
A
A
W
˚C
MIN.
-
MAX.
2
UNIT
kV
TYP.
-
55
MAX.
6.5
-
UNIT
K/W
K/W
April 1998
1
Rev 1.000