BUK556-60H Datasheet, PDF (1/7 Pages) NXP Semiconductors – PowerMOS transistor Logic level FET

Philips Semiconductors
PowerMOS transistor
Logic level FET
Product Specification
BUK556-60H
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope.
The device is intended for use in
automotive and general purpose
switching applications.
PINNING - TO220AB
PIN
DESCRIPTION
1 gate
2 drain
3 source
tab drain
QUICK REFERENCE DATA
SYMBOL PARAMETER
V_DS
I_D
P_tot
T_j
R_DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance;
V_GS = 5 V
PIN CONFIGURATION
SYMBOL
tab
g
1 23
MAX. UNIT
60 V
60 A
150 W
175 ˚C
22 mΩ
d
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DS
V_DGR
±V_GS
I_D
I_D
I_DM
P_tot
T_stg
T_j
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak
value)
Total power dissipation
Storage temperature
Junction Temperature
-
R_GS = 20 kΩ
-
T_mb = 25 ˚C
T_mb = 100 ˚C
T_mb = 25 ˚C
T_mb = 25 ˚C
-
-
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
R_{th j-mb}
R_{th j-a}
From junction to mounting base
From junction to ambient
MIN.
-
-
-
-
-
-
-
- 55
-
MAX.
60
60
15
60
44
240
150
175
175
UNIT
V
V
V
A
A
A
W
˚C
˚C
MIN.
-
-
TYP. MAX. UNIT
-
1.0 K/W
60
- K/W
October 1993
1
Rev 1.000