BUK482-200A Datasheet, PDF (1/8 Pages) NXP Semiconductors – PowerMOS transistor

Philips Semiconductors
PowerMOS transistor
Product specification
BUK482-200A
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a
plastic envelope suitable for surface
mounting featuring high avalanche
energy capability, stable blocking
voltage, fast switching and high
thermal cycling performance.
Intended for use in Switched Mode
Power Supplies (SMPS) and general
purpose switching applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
V_DS
I_D
P_tot
R_DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
MAX.
200
2.0
8.3
0.9
UNIT
V
A
W
Ω
PINNING - SOT223
PIN
DESCRIPTION
1 gate
2 drain
3 source
4 drain (tab)
PIN CONFIGURATION
4
1
2
3
SYMBOL
d
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DS
V_DGR
±V_GS
I_D
I_DM
I_DR
I_DRM
P_tot
T_stg
T_j
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (pulse peak
value)
Source-drain diode current
(DC)
Source-drain diode current
(pulse peak value)
Total power dissipation
Storage temperature
Junction Temperature
R_GS = 20 kΩ
T_sp = 25 ˚C
T_sp = 100 ˚C
T_sp = 25 ˚C
T_sp = 25 ˚C
T_sp = 25 ˚C
T_sp = 25 ˚C
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
W_DSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I_D = 2 A ; V_DD ≤ 50 V ; V_GS = 10 V ;
R_GS = 50 Ω
T_j = 25˚C prior to surge
T_j = 100˚C prior to surge
MIN.
-
-
-
-
-
-
-
-
-
-55
-
MIN.
-
-
MAX.
200
200
30
2.0
1.3
8.0
2.0
8.0
8.3
150
150
MAX.
50
8
UNIT
V
V
V
A
A
A
A
A
W
˚C
˚C
UNIT
mJ
mJ
January 1998
1
Rev 1.000