BUJ105AB Datasheet, PDF (1/7 Pages) NXP Semiconductors – Silicon Diffused Power Transistor

Philips Semiconductors
Silicon Diffused Power Transistor
Product specification
BUJ105AB
GENERAL DESCRIPTION
High-voltage, high-speed planar-passivated npn power switching transistor in SOT404 (D²-PAK) surface-mount
package intended for use in high frequency electronic lighting ballast applications, converters, inverters, switching
regulators, motor control systems, etc.
QUICK REFERENCE DATA
SYMBOL
V_CESM
V_CBO
V_CEO
I_C
I_CM
P_tot
V_CEsat
h_FEsat
t_f
PARAMETER
Collector-emitter voltage peak value
Collector-Base voltage (open emitter)
Collector-emitter voltage (open base)
Collector current (DC)
Collector current peak value
Total power dissipation
Collector-emitter saturation voltage
Fall time
CONDITIONS
V_BE = 0 V
T_mb ≤ 25 ˚C
I_C = 4.0 A;I_B = 0.8 A
I_C = 4.0 A; V_CE = 5 V
I_C = 5 A; I_B1 = 1 A
TYP.
-
-
-
-
-
-
0.3
11
20
MAX.
700
700
400
8
16
125
1.0
15
50
UNIT
V
V
V
A
A
W
V
ns
PINNING - SOT404
PIN
DESCRIPTION
1 base
2 collector
3 emitter
mb collector
PIN CONFIGURATION
mb
2
13
SYMBOL
c
b
e
LIMITING VALUES8
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_CESM
V_CEO
V_CBO
I_C
I_CM
I_B
I_BM
P_tot
T_stg
T_j
Collector to emitter voltage
Collector to emitter voltage (open base)
Collector to base voltage (open emitter)
Collector current (DC)
Collector current peak value
Base current (DC)
Base current peak value
Total power dissipation
Storage temperature
Junction temperature
V_BE = 0 V
T_mb ≤ 25 ˚C
THERMAL RESISTANCES
SYMBOL
R_{th j-mb}
R_{th j-a}
PARAMETER
Thermal resistance junction to mounting
base
Thermal resistance junction to ambient
CONDITIONS
minimum footprint, FR4 board
MIN.
-
-
-
-
-
-
-
-
-65
-
MAX.
700
400
700
8
16
4
8
125
150
150
UNIT
V
V
V
A
A
A
A
W
˚C
˚C
TYP. MAX. UNIT
-
1.0 K/W
55
- K/W
October 2001
1
Rev 1.000