74LVT125 Datasheet, PDF (1/15 Pages) NXP Semiconductors – 3.3V Quad buffer 3-State

74LVT125
3.3 V quad buffer; 3-state
Rev. 05 — 10 February 2005
Product data sheet
1. General description
The LVT125 is a high-performance BiCMOS product designed for V_CC operation at 3.3 V.
This device combines low static and dynamic power dissipation with high speed and high
output drive. The 74LVT125 device is a quad buffer that is ideal for driving bus lines. The
device features four output enable inputs (1OE, 2OE, 3OE and 4OE), each controlling one
of the 3-state outputs.
2. Features
s Quad bus interface
s 3-state buffers
s Output capability: +64 mA and −32 mA
s TTL input and output switching levels
s Input and output interface capability to systems at 5 V supply
s Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
s Live insertion and extraction permitted
s No bus current loading when output is tied to 5 V bus
s Power-up 3-state
s Latch-up protection:
x JESD78: exceeds 500 mA
s ESD protection:
x MIL STD 883 method 3015: exceeds 2000 V
x Machine model: exceeds 200 V
3. Quick reference data
Table 1: Quick reference data
GND = 0 V; T_amb = 25 °C.
Symbol Parameter
Conditions
t_PLH
propagation delay nA to nY C_L = 50 pF; V_CC = 3.3 V
t_PHL
propagation delay nA to nY C_L = 50 pF; V_CC = 3.3 V
C_I
input capacitance
V_I = 0 V or 3.0 V
C_O
output capacitance
outputs disabled;
V_O = 0 V or 3.0 V
I_CC
quiescent supply current outputs disabled;
V_CC = 3.6 V
Min Typ Max Unit
-
2.7 -
ns
-
2.9 -
ns
-
4
-
pF
-
8
-
pF
-
0.13 -
mA