74HC4053 Datasheet, PDF (1/33 Pages) NXP Semiconductors – Triple 2-channel analog multiplexer/demultiplexer

74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
Rev. 04 — 9 May 2006
Product data sheet
1. General description
The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A.
The 74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a
common enable input (E). Each multiplexer/demultiplexer has two independent
inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select
inputs (Sn).
With E LOW, one of the two switches is selected (low-impedance ON-state) by S1 to S3.
With E HIGH, all switches are in the high-impedance OFF-state, independent of S1 to S3.
V_CC and GND are the supply voltage pins for the digital control inputs (S1 to S3 and E).
The V_CC to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for
74HCT4053. The analog inputs/outputs (nY0 and nY1, and nZ) can swing between V_CC
as a positive limit and V_EE as a negative limit. V_CC − V_EE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, V_EE is connected to GND (typically
ground).
2. Features
s Low ON resistance:
x 80 Ω (typical) at V_CC − V_EE = 4.5 V
x 70 Ω (typical) at V_CC − V_EE = 6.0 V
x 60 Ω (typical) at V_CC − V_EE = 9.0 V
s Logic level translation:
x To enable 5 V logic to communicate with ±5 V analog signals
s Typical ‘break before make’ built in
s Complies with JEDEC standard no. 7A
s ESD protection:
x HBM EIA/JESD22-A114-C exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V
s Multiple package options
s Specified from −40 °C to +85 °C and from −40 °C to +125 °C