74F395 Datasheet, PDF (1/7 Pages) NXP Semiconductors – 4-bit cascadable shift register 3-State

Philips Semiconductors
4-bit cascadable shift register (3-State)
Product specification
74F395
FEATURES
• 4-bit parallel load shift register
• Independent 3-State buffer outputs, Q0–Q3
• Separate Qs output for serial expansion
• Asynchronous Master Reset
DESCRIPTION
The 74F395 is a 4-bit Shift Register with serial and parallel
synchronous operating modes and 3-State buffer outputs. The
shifting and loading operations are controlled by the state of the
Parallel Enable (PE) input. When PE is High, data is loaded from the
Parallel Data inputs (D0–D3) into the register synchronous with the
High-to-Low transition of the Clock input (CP). When PE is Low, the
data at the Serial Data input (Ds) is loaded into the Q0 flip-flop, and
the data in the register is shifted one bit to the right in the direction
(Q0!Q1!Q2!Q3) synchronous with the negative clock transition.
The PE and Data inputs are fully edge-triggered and must be stable
one setup prior to the High-to-Low transition of the clock.
The Master Reset (MR) is an asynchronous active-Low input. When
Low, the MR overrides the clock and all other inputs and clears the
register.
The 3-state output buffers are designed to drive heavily loaded
3-State buses, or large capacitive loads.
The active-Low Output Enable (OE) controls all four 3-State buffers
independent of the register operation. The data in the register
appears at the outputs when OE is Low. The outputs are in High
impedance “OFF” state, which means they will neither drive nor load
the bus when OE is High. The output from the last stage is brought
out separately. This output (Qs) is tied to the Serial Data input (Ds)
of the next register for serial expansion applications. The Qs output
is not affected by the 3-State buffer operation.
PIN CONFIGURATION
MR 1
Ds 2
D0 3
D1 4
D2 5
D3 6
PE 7
GND 8
16 V_CC
15 Q0
14 Q1
13 Q2
12 Q3
11 Qs
10 CP
9 OE
SF00940
TYPE
74F395
TYPICAL f_MAX
120MHz
TYPICAL SUPPLY CURRENT
(TOTAL)
32mA
ORDERING INFORMATION
DESCRIPTION
16-pin plastic DIP
COMMERCIAL RANGE
V_CC = 5V ±10%, T_amb = 0°C to +70°C
N74F395N
16-pin plastic SO
N74F395D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
D0 – D3
Data inputs
Ds
Serial data input
PE
Parallel Enable input
MR
Master Reset input (active Low)
OE
Output Enable input (active Low)
CP
Clock Pulse input (active falling edge)
Qs
Serial expansion output
Q0–Q3
Data outputs (3-State)
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
74F (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
150/40
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
3.0mA/24mA
1990 Oct 23
1
853–0370 00780