10H20EV8 Datasheet, PDF (1/17 Pages) NXP Semiconductors – ECL programmable array logic

Philips Semiconductors Programmable Logic Devices
ECL programmable array logic
Product specification
10H20EV8/10020EV8
DESCRIPTION
The 10H20EV8/10020EV8 is an ultra
high-speed universal ECL PAL^® device.
Combining versatile output macrocells with a
standard AND/OR single programmable
array, this device is ideal in implementing a
user’s custom logic. The use of Philips
Semiconductors state-of-the-art bipolar oxide
isolation process enables the
10H20EV8/10020EV8 to achieve optimum
speed in any design. The SNAP design
software package from Philips
Semiconductors simplifies design entry
based upon Boolean or state equations.
The 10H20EV8/10020EV8 is a two-level logic
element comprised of 11 fixed inputs, an
input pin that can either be used as a clock or
12th input, 90 AND gates, and 8 Output Logic
Macrocells. Each Output Macrocell can be
individually configured as a dedicated input,
dedicated output with polarity control, a
bidirectional I/O, or as a registered output
that has both output polarity control and
feedback to the AND array. This gives the
part the capability of having up to 20 inputs
and eight outputs.
The 10H20EV8/10020EV8 has a variable
number of product terms that can be OR’d
per output. Four of the outputs have 12 AND
terms available and the other four have 8
terms per output. This allows the designer the
extra flexibility to implement those functions
that he couldn’t in a standard PAL device.
Asynchronous Preset and Reset product
terms are also included for system design
ease. Each output has a separate output
enable product term. Another feature added
for the system designer is a power-up Reset
on all registered outputs.
The 10H20EV8/10020EV8 also features the
ability to Preload the registers to any desired
state during testing. The Preload is not
affected by the pattern within the device, so
can be performed at any step in the testing
sequence. This permits full logical verification
even after the device has been patterned.
FEATURES
• Ultra high speed ECL device
– t_PD = 4.5ns (max)
– t_IS = 2.6ns (max)
– t_CKO = 2.3ns (max)
– f_MAX = 208MHz
• Universal ECL Programmable Array Logic
– 8 user programmable output macrocells
– Up to 20 inputs and 8 outputs
– Individual user programmable output
polarity
• Variable product term distribution allows
increased design capability
• Asynchronous Preset and Reset capability
• 10KH and 100K options
• Power-up Reset and Preload function to
enhance state machine design and testing
• Design support provided via SNAP and
other CAD tools
• Security fuse for preventing design
duplication
• Available in 24-Pin 300mil-wide DIP and
28-Pin PLCC.
PIN CONFIGURATIONS
F Package
I₁ 1
I₂ 2
CLK/I₁₂ 3
F₁ 4
F₂ 5
V_CO1 6
F₃ 7
F₄ 8
I₃ 9
I₄ 10
I₅ 11
V_EE ¹²
F = Ceramic DIP (300mil-wide)
24 V_CC
23 I₁₁
22 I₁₀
21 F₈
20 F₇
19 V_CO2
18 F₆
17 F₅
16 I₉
15 I₈
14 I₇
13 I₆
A Package
CLK/I₁₂ I₂ I₁ NC V_CC I₁₁ I₁₀
4 3 2 1 28 27 26
F₁ 5
F₂ 6
V_CO1 7
NC 8
25 F₈
24 F₇
23 V_CO2
22 NC
F₃ 9
21 _F6
F₄ 10
20 F₅
I₃ 11
19 I₉
12 13 14 15 16 17 18
I₄ I₅ V_EE NC I₆ I₇ I₈
A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION
24-Pin Ceramic Dual In-Line (300mil-wide)
28-Pin Plastic Leaded Chip Carrier
ORDER CODE
10H20EV8–4F
10020EV8–4F
10H20EV8–4A
10020EV8–4A
DRAWING NUMBER
0586B
0401F
®PAL is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices, Inc.
October 22, 1993
113
853–1423 11164