PI7C7300D Datasheet, PDF (9/107 Pages) Pericom Semiconductor Corporation – 3-PORT PCI-to-PCI BRIDGE

PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
LIST OF TABLES
TABLE 4-1 PCI TRANSACTIONS ........................................................................................................... 21
TABLE 4-2 WRITE TRANSACTION FORWARDING ........................................................................... 23
TABLE 4-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES ............................... 26
TABLE 4-4 READ PREFETCH ADDRESS BOUNDARIES ................................................................... 29
TABLE 4-5 READ TRANSACTION PREFETCHING ............................................................................. 30
TABLE 4-6 DEVICE NUMBER TO IDSEL S1_AD OR S2_AD PIN MAPPING ................................... 34
TABLE 4-7 DELAYED WRITE TARGET TERMINATION RESPONSE .............................................. 39
TABLE 4-8 RESPONSE TO POSTED WRITE TARGET TERMINATION............................................ 39
TABLE 4-9 RESPONSE TO DELAYED READ TARGET TERMINATION.......................................... 40
TABLE 6-1 SUMMARY OF TRANSACTION ORDERING.................................................................... 50
TABLE 7-1 SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT ................... 58
TABLE 7-2 SETTING SECONDARY INTERFACE DETECTED PARITY ERROR BIT...................... 58
TABLE 7-3 SETTING PRIMARY INTERFACE DATA PARITY ERROR DETECTED BIT................ 59
TABLE 7-4 SETTING SECONDARY INTERFACE DATA PARITY ERROR DETECTED BIT.......... 59
TABLE 7-5 ASSERTION OF P_PERR#.................................................................................................... 60
TABLE 7-6 ASSERTION OF S_PERR#.................................................................................................... 62
TABLE 7-7 ASSERTION OF P_SERR# FOR DATA PARITY ERRORS ............................................... 62
TABLE 16-1 TAP PINS.............................................................................................................................. 99
TABLE 16-2 JTAG BOUNDARY REGISTER ORDER ......................................................................... 101
LIST OF FIGURES
FIGURE 9-1 SECONDARY ARBITER EXAMPLE.................................................................................. 68
FIGURE 16-1 TEST ACCESS PORT BLOCK DIAGRAM....................................................................... 98
FIGURE 17-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS .............................................. 105
FIGURE 18-1 272-PIN PBGA PACKAGE............................................................................................... 107
Pericom Semiconductor
Page 9 of 107
November 2005 - Revision 1.01