PI7C7300D Datasheet, PDF (81/107 Pages) Pericom Semiconductor Corporation – 3-PORT PCI-to-PCI BRIDGE

PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
14.1.17
14.1.18
Bit
Function
Type Description
Set to 1 (by a target device) whenever a target abort cycle occurs on
27
Signaled Target
Abort
R/WC
its secondary (S1 or S2) interface
Reset to 0
Set to 1 (by a master device) whenever transactions on its secondary
28
Received Target
Abort
R/WC
(S1 or S2) interface are terminated with target abort
Reset to 0
Set to 1 (by a master) when transactions on its secondary (S1 or S2)
29
Received Master
Abort
R/WC
interface are terminated with Master Abort
Reset to 0
30
Received System
Error
R/WC
Set to 1 when S1_SERR# or S2_SERR# is asserted
Reset to 0
Set to 1 when address or data parity error is detected on the
31
Detected Parity
Error
R/WC ^{secondary (S1 or S2) interface}
Reset to 0
MEMORY BASE REGISTER – OFFSET 20h
Bit
Function
3:0
15:4 Memory Base
Address [15:4]
Type
R/O
R/W
Description
Lower four bits of register are read only and return 0.
Reset to 0
Defines the bottom address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be 0.
Reset to 0
MEMORY LIMIT REGISTER – OFFSET 20h
Bit
Function
19:16
Type
R/O
31:20 Memory Limit
R/W
Address [31:20]
Description
Lower four bits of register are read only and return 0.
Reset to 0
Defines the top address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be FFFFFh.
Pericom Semiconductor
Page 81 of 107
November 2005 - Revision 1.01