PI7C8148B_06 Datasheet, PDF (81/94 Pages) Pericom Semiconductor Corporation – ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

PI7C8148B
ASYNCHRONOUS 2-PORT
PCI-TO-PCI BRIDGE
Bit
Function
Type Description
S_CLKOUT[3] (slot 3) Enable
00: enable S_CLKOUT[3]
7:6
Clock 3 disable RW
01: enable S_CLKOUT[3]
10: enable S_CLKOUT[3]
11: disable S_CLKOUT[3] and driven LOW
Reset to 00
S_CLKOUT[4] (device 1) clock enable
8
Clock 4 disable RW
0: enable S_CLKOUT[4]
1: disable S_CLKOUT[4] and driven LOW
13:9 Reserved
15:14 Reserved
Reset to 0
RO
Reserved. Reset to 1Fh
RO
Reserved. Reset to 00
15.2.35 P_SERR# STATUS REGISTER – OFFSET 68h
Bit
Function
Type Description
1: Signal P_SERR# was asserted because an address parity error was detected on
16
Address Parity
Error
RWC ^{P or S bus.}
Reset to 0
17
Posted Write
Data Parity
1: Signal P_SERR# was asserted because a posted write data parity error was
RWC ^{detected on the target bus.}
Error
Reset to 0
1: Signal P_SERR# was asserted because the bridge was unable to deliver post
18
Posted Write
Non-delivery
RWC ^{memory write data to the target after 224 attempts.}
Reset to 0
19
Target Abort
during Posted
1: Signal P_SERR# was asserted because the bridge received a target abort when
RWC ^{delivering post memory write data.}
Write
Reset to 0.
20
Master Abort
during Posted
1: Signal P_SERR# was asserted because the bridge received a master abort when
RWC ^{attempting to deliver post memory write data}
Write
Reset to 0.
1: Signal P_SERR# was asserted because the bridge was unable to deliver
21
Delayed Write
Non-delivery
RWC ^{delayed write data after 224 attempts.}
Reset to 0
22
Delayed Read –
No Data from RWC
1: Signal P_SERR# was asserted because the bridge was unable to read any data
from the target after 2²⁴ attempts.
Target
Reset to 0.
Delayed
23
Transaction
1: Signal P_SERR# was asserted because a master did not repeat a read or write
RWC ^{transaction before master timeout.}
Master Timeout
Reset to 0.
06-0053
Page 81 of 94
APRIL 2006 – Revision 1.05