PI7C8148B_06 Datasheet, PDF (34/94 Pages) Pericom Semiconductor Corporation – ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

PI7C8148B
ASYNCHRONOUS 2-PORT
PCI-TO-PCI BRIDGE
Table 2-8. Response to Posted Write Target Termination
Target Termination
Normal
Target Retry
Target Disconnect
Target Abort
Repsonse
No additional action.
Repeating write transaction to target.
Initiate write transaction for delivering remaining posted write data.
Set received-target-abort bit in the target interface status register. Assert
P_SERR# if enabled, and set the signaled-system-error bit in primary status
register.
Note that when a target retry or target disconnect is returned and posted write data associated with that
transaction remains in the write buffers, the bridge initiates another write transaction to attempt to
deliver the rest of the write data. If there is a target retry, the exact same address will be driven as for
the initial write trans-action attempt. If a target disconnect is received, the address that is driven on a
subsequent write transaction attempt will be updated to reflect the address of the current DWORD. If
the initial write transaction is Memory-Write-and-Invalidate transaction, and a partial delivery of write
data to the target is performed before a target disconnect is received, the bridge will use the memory
write command to deliver the rest of the write data. It is because an incomplete cache line will be
transferred in the subsequent write transaction attempt.
After the bridge makes 2²⁴ (default) write transaction attempts and fails to deliver all posted write data
associated with that transaction, the bridge asserts P_SERR# if the primary SERR# enable bit is set (bit
8 of command register for secondary bus) and posted-write-non-delivery bit is not set. The posted-
write-non-delivery bit is the bit 2 of P_SERR# event disable register (offset 64h). The bridge will report
system error. See Section 5.4 for a discussion of system error conditions.
2.8.3.3 DELAYED READ TARGET TERMINATION RESPONSE
When the bridge initiates a delayed read transaction, the abnormal target responses can be passed back
to the initiator. Other target responses depend on how much data the initiator requests. Table 2-9 shows
the response to each type of target termination that occurs during a delayed read transaction.
The bridge repeats a delayed read transaction until one of the following conditions is met:
Bridge completes at least one data transfer.
Bridge receives a master abort.
Bridge receives a target abort.
The bridge makes 2²⁴ (default) read attempts resulting in a response of target retry.
Table 2-9. Response to Delayed Read Target Termination
Target Termination
Response
Normal
If prefetchable, target disconnect only if initiator requests more data than read from target. If
non-prefetchable, target disconnect on first data phase.
Target Retry
Re-initiate read transaction to target
Target Disconnect
If initiator requests more data than read from target, return target disconnect to initiator.
Target Abort
Return target abort to initiator. Set received target abort bit in the target interface status
register. Set signaled target abort bit in the initiator interface status register.
After the bridge makes 2²⁴(default) attempts of the same delayed read transaction on the target bus, the
bridge asserts P_SERR# if the primary SERR# enable bit is set (bit 8 of command register for
secondary bus) and the delayed-write-non-delivery bit is not set. The delayed-write-non-delivery bit is
bit 5 of P_SERR# event disable register (offset 64h). The bridge will report system error. See Section
5.4 for a description of system error conditions.
06-0053
Page 34 of 94
APRIL 2006 – Revision 1.05