PI3VDP411LSA Datasheet, PDF (8/13 Pages) Pericom Semiconductor Corporation – Dual Mode DisplayPort to DVI/HDMI Electrical bridge (Level Shifter)

PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifter)
Table: Differential Input Characteristics forIN_Dx signals
Symbol
Parameter
Min Typ Max Units
Tbit
UI, Unit Interval
360
ps
VRX_DIFF
TRX_EYE
VCM-ACp-p
ZRX_DC
ZRX-Bias
ZRX_HIGH-Z
Input Differential Volt-
age Level
Minimum Eye Width at
IN_D input pair
AC Peak Common
Mode Input Voltage
0.175
0.8
40 50
1.200 V
Tbit
100 mV
60 Ω
0
2.0 V
100
kΩ
Comments
Tbit is determined by the display mode. Nominal
bit rate ranges from 250Mbps to 2.5Gbps per lane.
Nominal Tbit at 2.5 Gbps = 400 ps. 360ps = 400ps-
10%
See note 1 below
See note 2 below
Required IN_D+ as well as IN_D- DC impedance
(50 ±20% tolerance).
Intended to limit power-up stress on chipset's PCIE
output buffers.
Differential inputs must be in a high impedance
state when OE# is HIGH.
1. VRX-DIFF = 2x|VRX-D- -VRX-D-| Applies to IN_Dx signals
2. VCM-AC-p-p = |VRX-D- - VRX-D-|/2 - VRX-CM-DC
VRX-CM-DC = DC(avg) of |VRX-D+ + VRX-D-|/2
VCM-AC-p-p includes all frequencies above 30 kHz.
TMDS Outputs
The level shifter's TMDS outputs are required to meet HDMI 1.3 specifications.
The HDMI 1.3 Specification is assumed to be the correct reference in instances where this document conflicts with the HDMI 1.3
specification.
12-0236
8
www.pericom.com
PS9059A
07/28/12