PI3VDP411LSA Datasheet, PDF (6/13 Pages) Pericom Semiconductor Corporation – Dual Mode DisplayPort to DVI/HDMI Electrical bridge (Level Shifter)

PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifter)
Truth Table (Slew Rate control function)
SR1
SR0
1
1
1
0
0
1
0
0
Rise/Fall Time (Typ)
140ps
130ps
120ps
110ps
Test Setup Condition
VDD = 3.3V, Ambient temperature 25°C
Rise/Fall time is from 20% to 80% on Rising/Falling edge
Date rate: 620 Mbps
Input: 1V differential peak-to-peak clock pattern
Equalization : 3dB
Table 1: OE Pin Description
OE#
Device State
Comments
Asserted (low voltage)
Unasserted (high voltage)
Differential input buffers and output buffers
enabled. Input impedance = 50Ω
Low-power state.
àà Differential input buffers and termination
are disabled.
àà Differential inputs are in a high
impedance state.
àà OUT_D level-shifting outputs are
disabled.
àà OUT_D level-shifting outputs are in high
impedance state.
àà Internal bias currents are turned off.
Normal functioning state for IN_D to OUT_D
level shifting function.
Intended for lowest power condition when:
àà No display is plugged in or
àà The level shifted data path is disabled
HPD_SINK input and HPD_SOURCE
output are not affected by OE# SCL_
SOURCE, SCL_SINK, SDA_SOURCE
and SDA_SINK signals and functions
are not affected by OE#
12-0236
6
www.pericom.com
PS9059A
07/28/12