PI7C8152A_07 Datasheet, PDF (76/90 Pages) Pericom Semiconductor Corporation – 2-Port PCI-to-PCI Bridge

PI7C8152A & PI7C8152B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Bit
Function
22
Secondary
Interface Reset
23
Fast Back-to-
Back Enable
24
Primary Master
Timeout
25
Secondary
Master Timeout
26
Master Timeout
Status
27
Discard Timer
P_SERR_L
enable
31-28 Reserved
Type
R/W
Description
Controls the assertion of S_RESET_L signal pin on the secondary
interface
0: does not force the assertion of S_RESET_L pin
1: forces the assertion of S_RESET_L
Reset to 0
R/W Controls bridge’s ability to generate fast back-to-back transactions to
different devices on the secondary interface.
0: does not generate fast back-to-back transactions on the secondary
1: enables fast back-to-back transaction generation on the secondary
Reset to 0
R/W Determines the maximum number of PCI clock cycles the
PI7C8152x waits for an initiator on the primary interface to repeat a
delayed transaction request.
0: Primary discard timer counts 2¹⁵ PCI clock cycles.
1: Primary discard timer counts 2¹⁰ PCI clock cycles.
Reset to 0
R/W Determines the maximum number of PCI clock cycles the
PI7C8152x waits for an initiator on the primary interface to repeat a
delayed transaction request.
0: Primary discard timer counts 2¹⁵ PCI clock cycles.
1: Primary discard timer counts 2¹⁰ PCI clock cycles.
R/WC
Reset to 0
This bit is set to 1 when either the primary master timeout counter or
secondary master timeout counter expires.
Reset to 0
R/W This bit is set to 1 and P_SERR_L is asserted when either the
primary discard timer or the secondary discard timer expire.
0: P_SERR_L is not asserted on the primary interface as a result of
the expiration of either the Primary Discard Timer or the Secondary
Discard Timer.
1: P_SERR_L is asserted on the primary interface as a result of the
expiration of either the Primary Discard Timer or the Secondary
Discard Timer.
Reset to 0
R/O Reserved. Returns 0 when read. Reset to 0.
12.1.28
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h
Bit
Function
0
Reserved
Type Description
R/O Reserved. Returns 0 when read. Reset to 0
Page 76 of 90
October 16, 2003 – Revision 1.11