PI7C8152A_07 Datasheet, PDF (69/90 Pages) Pericom Semiconductor Corporation – 2-Port PCI-to-PCI Bridge

12.1.4
PI7C8152A & PI7C8152B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Bit
Function
8
P_SERR_L
enable
9
Fast Back-to-
Back Enable
15:10 Reserved
Type
R/W
R/W
R/O
Description
Controls the enable for the P_SERR_L pin
0: disable the P_SERR_L driver
1: enable the P_SERR_L driver
Reset to 0
Controls PI7C8152x’s ability to generate fast back-to-back
transactions to different devices on the primary interface.
0: no fast back-to-back transactions
1: enable fast back-to-back transactions
Reset to 0
Returns 000000 when read
PRIMARY STATUS REGISTER – OFFSET 04h
Bit
19:16
20
Function
Reserved
Capabilities List
Type
R/O
R/O
21
66MHz Capable R/O
22
Reserved
R/O
23
Fast Back-to-
R/O
Back Capable
24
Data Parity Error R/WC
Detected
26:25 DEVSEL_L
R/O
timing
27
Signaled Target R/WC
Abort
28
Received Target R/WC
Abort
29
Received Master R/WC
Abort
30
Signaled System R/WC
Error
Description
Reset to 0
Set to 1 to enable support for the capability list (offset 34h is the
pointer to the data structure)
Reset to 1
Set to 1 to indicate the primary may be run at 66MHz operation
Reset to 1
Reset to 0
Set to 1 to enable decoding of fast back-to-back transactions on the
primary interface to different targets
Reset to 1
Set to 1 when P_PERR_L is asserted and bit 6 of command register
is set
Reset to 0
DEVSEL_L timing (medium decoding)
00: fast DEVSEL_L decoding
01: medium DEVSEL_L decoding
10: slow DEVSEL_L decoding
11: reserved
Reset to 01
Set to 1 (by a target device) whenever a target abort cycle occurs
Reset to 0
Set to 1 (by a master device) whenever transactions are terminated
with target aborts
Reset to 0
Set to 1 (by a master) when transactions are terminated with Master
Abort
Reset to 0
Set to 1 when P_SERR_L is asserted
Reset to 0
Page 69 of 90
October 16, 2003 – Revision 1.11