PI2DBS6212 Datasheet, PDF (6/7 Pages) Pericom Semiconductor Corporation – 6.5 Gbps SAS2, SATA3, XAUI 2 Differential Channel, 2:1 Mux/DeMux Switch

PI2DBS6212
6.0 Gbps SAS2, SATA3, XAUI
2 Differential Channel, 2:1 Mux/DeMux Switch
+
BALANCED
PORT1
–
DUT
BALANCED
PORT2
+
BALANCED
PORT1
–
DUT
50
50
BALANCED
PORT2
Diff. Insertion Loss and Return Test
Circuit
Diff. Off Isolation Test Circuit
+
50
BALANCED
PORT1
–
50
+
50
BALANCED
PORT2
–
50
DUT
Diff. Near End Xtalk Test Circuit
Test Circuit for Electrical Characteristics^(1-5)
VDD
2 x VDD
200-Ohm
Pulse
VIN
Generator
VOUT
D.U.T
4pF
RT
CL
200-Ohm
Switch Positions
Test
t_PLZ, t_PZL
t_PHZ, t_PZH
Prop Delay
Switch
2 x V_DD
GND
Open
Notes:
1. C_L = Load capacitance: includes jig and probe capacitance.
2. R_T = Termination resistance: should be equal to Z_OUT of the Pulse Generator
3. Output 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
output 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
4. All input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, Z_O = 50Ω, t_R ≤ 2.5ns, t_F ≤ 2.5ns.
5. The outputs are measured one at a time with one transition per measurement.
Switching Waveforms
SEL
tPZL
Output
tPZH
Output
V_DD/2
V_DD/2
tPLZ
V_DD/2
tPHZ
V_DD/2
V_OL +0.3V
V_OH –0.3V
V_DD
0V
VOH
VOL
VOH
VOL
Voltage Waveforms Enable and Disable Times
14-0031
6
www.pericom.com
03/26/2014