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PT7C433833 Datasheet, PDF (5/17 Pages) Pericom Semiconductor Corporation – Real-time Clock Module (I2C Bus)
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PT7C433833
Real-time Clock Module (I2C Bus)
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(TA = -40℃ to +85℃) (Note 1)
Parameter
Symbol
Conditions
Min.
Typ.
Max. Unit
SCL Clock Frequency
Fast mode
100
fSCL
Standard mode
-
-
400
kHz
-
100
Bus Free Time Between STOP and
Fast mode
1.3
-
-
START condition
tBUF
Standard mode
4.7
-
μs
-
Hold Time (Repeated) START Condition
Fast mode
0.6
-
-
(Note 2)
tHD:STA
Standard mode
4.0
-
-
μs
LOW Period of SCL Clock
Fast mode
1.3
-
-
tLOW
Standard mode
4.7
-
-
μs
HIGH Period of SCL Clock
Fast mode
0.6
-
-
tHIGH
Standard mode
4.0
-
-
μs
Setup Time of Repeated START
Fast mode
0.6
-
-
Condition
tSU:STA
Standard mode
4.7
-
-
μs
Data Hold Time (Note 3, 4)
Fast mode
0
tHD:STA
Standard mode
0
-
0.9
-
-
μs
Data Setup Time (Note 5)
Fast mode
100
-
tSU:STA
Standard mode
250
-
-
ns
-
Rise Time of Both SDA and SCL Signals
(Note 6)
Fall Time of Both SDA and SCL Signals
(Note 6)
Setup Time for STOP Condition
tr
tf
tSU:STO
Fast mode
20+0.1CB
-
Standard mode
20+0.1CB
-
Fast mode
20+0.1CB
-
Standard mode
20+0.1CB
-
Fast mode
0.6
-
Standard mode
4.0
-
300
1000
ns
300
300
ns
-
μs
-
Capacitance Load for Each Bus Line
CB
Note 6
-
-
400
pF
I/O Capacitance (SDA, SCL)
CI/O
Note 1
-
-
10
pF
Oscillator Stop Flag (OSF) Delay
tOSF
Note 7
-
100
-
ms
Note 1: Limits of full temperature are guaranteed by design not production test.
Note 2: After this period, the first clock pulse is generated.
Note 3: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal)
to bridge the undefined region of the falling edge of SCL.
Note 4: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 5: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr MAX + tSU:DAT = 1000 + 250 =
1250ns before the SCL line is released.
Note 6: CB------total capacitance of one bus line in pF.
Note 7: The parameter tOSF is the time period the oscillator must be stopped for the OSF flag to be set over the voltage range of
0.0V ≤ VCC ≤ VCC MAX and 1.3V ≤ VBAT ≤ 3.7V.
12-07-0001
PT0321-6 07/04/12
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