PT7C4512 Datasheet, PDF (4/5 Pages) Pericom Semiconductor Corporation – PLL Clock Multiplier

PT7C4511
PLL Clock Multiplier
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AC Electrical Characteristics
(V_CC = 3.3V±0.3V, T_A = -40 ~ 85ºC, unless otherwise noted)
Sym.
Parameter
Test Condition
Pin
f_IN
Input Frequency
Crystal
Clock
ICLK
ICLK
f_OUT Output Frequency**
t_R
Output clock rise time
t_F
Output clock fall time
Duty Output clock duty cycle
PLL bandwidth*
Vcc: 3.0 to 3.6V
0.8 to 2.0V, with 15pF
load
2.0 to 0.8V, with 15pF
load
At Vcc/2, below
160MHz
At Vcc/2, 160MHz to
180MHz
-
CLK
CLK
CLK
CLK
CLK
-
Period Jitter
70MHz~160MHz, 25C CLK
Note:
*: Only reference for design
**: The phase relationship between input and output clocks can change at power up.
(V_CC = 5.0V±0.5V, T_A = -40 ~ 85ºC, unless otherwise noted)
Sym.
Parameter
Test Condition
Pin
f_IN
Input Frequency
Crystal
Clock
ICLK
ICLK
f_OUT Output Frequency**
t_R
Output clock rise time
t_F
Output clock fall time
Duty Output clock duty cycle
PLL bandwidth*
Vcc: 4.5 to 5.5V
20%Vcc to 80%Vcc,
with 15pF load
80%Vcc to 20%Vcc,
with 15pF load
At Vcc/2,
below160MHz
At Vcc/2, 160MHz to
200MHz
-
CLK
CLK
CLK
CLK
CLK
-
Period Jitter
70MHz~200MHz, 25C CLK
Note:
*: Only reference for design
**: The phase relationship between input and output clocks can change at power up.
Min.
5
4
20
-
-
45
40
10
-
Min.
5
4
20
-
-
45
40
10
-
Typ. Max. Unit
-
40
MHz
-
50
MHz
-
180
MHz
1
-
ns
1
-
ns
50
55
%
60
%
-
-
kHz
-
120
ps
Typ. Max. Unit
-
40
MHz
-
50
MHz
-
200
MHz
1.2
-
ns
1.2
-
ns
50
55
%
60
%
-
-
kHz
-
120
ps
2014-08-0003
PT0152-7
08/14/14
4