PT7C4512 Datasheet, PDF (1/5 Pages) Pericom Semiconductor Corporation – PLL Clock Multiplier

PT7C4512
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PLL Clock Multiplier
Features
Description
 Zero ppm multiplication error
 Input crystal frequency of 5 - 40 MHz
 Input clock frequency of 4 - 50 MHz
 Output clock frequencies up to 200 MHz
 Low period jitter 80ps (100~200MHz)
 Duty cycle of 45/55% of output clock up to 160MHz
 9 selectable frequencies controlled by S0, S1 pins
 Operating voltages of 3.0 to 5.5V
 Lead free SOIC-8 package
This Clock Multiplier is the most cost-effective way to
generate a high quality, high frequency clock outputs
from lower frequency crystal or clock input. It is
designed to replace crystal oscillators in most electronic
systems, clock multipliers and frequency translation
devices with low output jitter. The device implements a
standard fundamental mode using PLL techniques and
inexpensive crystal to produce output clocks up to 200
MHz.
Pin Configuration
The internal Logic divider is to generate nine different
popular multiplication factors, allowing one chip to
1 X1/ICLK
2 Vcc
3 GND
X2 8
S1 7
S0 6
output many common frequencies.
4 REF
CLK 5
SOIC-8 package
Pin Description
Name
X1/ICLK
Vcc
GND
REF
CLK
S0
S1
X2
Pin No.
1
2
3
4
5
6
7
8
Type
X1
P
P
O
O
T1
T1
XO
Description
Crystal connection or clock input.
Connect to +3.3V or +5V.
Connect to ground.
Buffered crystal oscillator output
clock
Clock output per Clock Output
Table.
Multiplier select pin 0, connect to
GND or Vcc or floating (no
connection).
Multiplier select pin 1, connect to
GND or Vcc or floating (no
connection).
Crystal connection. Leave
unconnected for clock input.
Clock Output Table
S1
S0
CLK
0
0
×4¹⁾
0
M²⁾
×(16/3)
0
1
×5
M
0
×2.5
M
M
×2
M
1
×(10/3)
1
0
×6
1
M
×3
1
1
×8
1) Note: CLK output frequency=ICLK×4.
2) Note: M=Leave unconnected (self-biases to
Vcc/2).
2014-08-0003
PT0152-7
08/14/14
1