PI6C49004 Datasheet, PDF (4/12 Pages) Pericom Semiconductor Corporation – Networking Clock Generator

PI6C49004
Networking Clock Generator
Serial Data Interface (SMBus)
PI6C49004 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit ad-
dress and read/write bit as shown below.
Address Assignment
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
0/1
How to Write
1 bit 8 bits
1
8 bits
1
8 bits
1
8 bits
1
8 bits
Start
bit
Note:
1.
D2H
Ack
Register
offset
Ack
Byte
Count = N
Ack
Data Byte
0
Ack
…
Data Byte
N-1
Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
1
Ack
1 bit
Stop bit
How to Read (M: abbreviation for Master or Controller; S: abbreviation for slave/clock)
1 bit 8 bits 1 bit 8 bits 1 bit 1 bit 8 bits 1 bit 8 bits 1 bit 8 bits 1 bit … 8 bits 1 bit 1 bit
S:
M: send
M: M:
S: starting S:
M:
Start Send sends databyte sends Start
bit "D2h" Ack location: Ack bit
N
M:
Send
"D3h"
S:
sends
Ack
sends
# of
data
bytes
that
will
be
sent:
M:
sends
Ack
S:
sends
start-
ing
data
byte
N
M:
sends
Ack
…
S:
sends
data
byte
N+X-
1
M:
Not
Ac-
knowl-
edge
M:
Stop
bit
X
Byte 0: Spread Spectrum Control Register
Bit Description
Type
7
Spread Spectrum Selection for 100MHz HCSL
PCI-Express clocks
RW
6
Enables hardware or software control of OE bits
(see Byte 0–Bit 6 and Bit 5 Functionality table)
RW
Software PD_RESET bit. Enables or disables all
5
outputs
RW
(see Byte 0–Bit 6 and Bit 5 Functionality table)
4
Frequency margining select bit FS3
RW
3
Frequency margining select bit FS2
RW
2
Frequency margining select bit FS1
RW
1
Frequency margining select bit FS0
RW
0
OE for single-ended 50MHz output 50M_Out2 RW
Power Up
Condition
0
0
1
1
0
1
0
1
Output(s)
Affected
All 100MHz HCSL
PCI Express outputs
PD_RESET pin,
bit 5
Notes
0=spread off
1 = -0.5% down
spread
0 = hardware cntl
1 = software ctrl
All outputs
0 = disabled
1 = enabled
50M_Out1 and
50M_Out2
Single-ended
50MHz output
50M_Out2
See 50MHz Frequen-
cy Margining Table
on Page 3
0 = disabled
1 = enabled
11-0080
09-0098
4
PS9047A
04/11/11