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PI3L100 Datasheet, PDF (3/6 Pages) Pericom Semiconductor Corporation – 3.3V, Wide Bandwidth Quad 2:1 Mux/Demux LanSwitch
PI3L100
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Power Supply Characteristics
Parameters Description
ICC
Quiescent Power
Supply Current
∆ICC
Supply Current per
Input @ TTL HIGH
ICCD
Supply Current per
Input per MHz(4)
Test Conditions(1)
VCC = Max.
VIN = GND or VCC
VCC = Max.
VIN = 3.4V(3)
VCC = Max.,
Input Pins Open
E = GND
Control Input Toggling
50% Duty Cycle
Min. Typ(2) Max. Units
— 0.1 3.0 µA
—
— 750 µA
— — 0.25 mA/
MHz
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input (VIN = 3.0V, control inputs only); A and B pins do not contribute to ICC.
4. This current applies to the control inputs only and represent the current required to switch internal capacitance at the specified
frequency. The A and B inputs generate no significant AC or DC currents as they transition. This parameter is not tested, but is
guaranteed by design.
Switching Characteristics over Operating Range
Parameters
tPLH
tSY
tPHZ
tPLZ
XTALK
Description
Propagation Delay(2,3)
In to Y
Bus Enable Time
S to Y
Bus Disable Time
E to Y
Crosstalk
OIRR
BW
tON
tOFF
Off Isolation
–3dB Bandwidth
Turn On Time
Turn Off Time
Conditions(1)
CL = 50pF
RL = 500Ω
RL = 100Ω
f = 30 MHz
See Figure 2
RL = 100Ω
f = 30 MHz
RL = 100Ω
See Figure 2
RL = 100Ω
CL = 35pF
See Figure 1
PI3L100
Com.
Min Typ Max
— — 0.25
1
— 4.5
1
— 4.5
— –90 —
— –45 —
— 213 —
———
———
Unit
ns
ns
ns
dB
dB
MHz
ns
ns
Notes:
1. See test circuit and waveforms.
2. This parameter is guaranteed but not tested.
3. The bus switch contributes no propagational delay other than the RC delay of the ON resistance of
the switch and the load capacitance. The time constant for the switch alone is of the order of 0.25ns
for 50pF load. Since this time constant is much smaller than the rise/fall times of typical driving
signals, it adds very little propagational delay to the system. Propagational delay of the bus switch
when used in a system is determined by the driving circuit on the driving side of the switch and its
interaction with the load on the driven side.
3
PS8504 11/13/00