PT7M6315US Datasheet, PDF (2/6 Pages) Pericom Semiconductor Corporation – Supervisory Circuit

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Block Diagram
Vcc
VCC Resistor
Divider
T.C.
Reference
PT7M6315US
Supervisory Circuit
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Timing
Delay
MR
RST
GND
Function Description
Power Monitor
A microprocessor’s (µP’s) reset input starts the µP in a known state. Whenever the µP is in an unknown state, it should be held in
reset. The supervisory circuits assert reset during power-up and prevent code execution errors during power-down or brownout
conditions.
On power-up, once Vcc reaches about 1.0V, RST is a guaranteed logic low of 0.4V or less. As Vcc rises, RST stays low. When
Vcc rises above the reset threshold V_RST, an internal timer releases RST after about 200ms (PT7M6315USxxD3) or 1570ms
(PT7M6315USxxD4) or 26ms (PT7M6315USxxD2) or 1.6ms (PT7M6315USxxD1). RST asserts whenever Vcc drops below the
reset threshold, i.e. brownout condition. If brownout occurs in the middle of a previously initiated reset pulse, the pulse continues
for at least another 200ms (PT7M6315USxxD3) or 1570ms (PT7M6315USxxD4) or 26ms (PT7M6315USxxD2) or 1.6ms
(PT7M6315USxxD1). On power-down, once Vcc falls below the reset threshold, RST stays low and is guaranteed to be 0.4V or
less until Vcc drops below 1V.
Manual Reset
The manual-reset input (MR) allows reset to be triggered by a pushbutton switch. The switch is effectively debounced by the
1.6ms (PT7M6315USxxD1) or 26ms (PT7M6315USxxD2) or 200ms (PT7M6315USxxD3) or 1570ms (PT7M6315USxxD4)
reset pulse width.
2015-09-0002
PT0197-4 09/15/15
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