PI6CV855 Datasheet, PDF (2/9 Pages) Pericom Semiconductor Corporation – PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory

PI6CV855
PLL Clock Driver for 2.5V
SSTL 2 DDR SDRAM Memory _{1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122}
Pinout Table
Pin
Name
Pin No.
I/O
Type
Description
CLK
5
CLK
6
I Reference Clock input
Y[0:4] 3,11,13,17,27
Clock outputs.
Y[0:4] 2,10,14,16,28
FBOUT
23
FBOUT
24
O ^{Complement Clock outputs.}
Feedback output, and Complement Feedback Output
FBIN
21
FBIN
20
I Feedback input, and Complement Feedback input
V_DDQ
AV_DD
4,12,18,22,26
7
Power
Power Supply for I/O pins.
Analog/core power supply. AV_DD can be used to bypass the PLL for testing purposes. When
AV_DD is strapped to ground, PLL is bypassed & CLK is buffered directly to the device outputs.
AGND
GND
8
Analog/core ground. Provides the ground reference for the analog/core circuitry
Ground
1,9,15,19,25
Ground for I/O pins.
Function Table
AV_DD
GND
GND
2.5V(nom)
2.5V(nom)
2.5V(nom)
Inputs
CLK
CLK
L
H
H
L
L
H
H
L
<20 MHz
Y[0:4]
Z
Z
L
H
Z
Outputs
Y[0:4]
FBOUT
Z
Z
Z
Z
H
L
L
H
Z
Z
FBOUT
Z
Z
H
L
Z
PLL State
Bypassed/Off
Bypassed/Off
on
on
off
Notes: For testing and power saving purposes, PI6CV855 will power down if the frequency of the reference inputs
CLK, CLK is well below the operating frequency range. The maximum power down clock frequency is below 20 MHz.
For example, PI6CV855 will be powered down when the CLK,CLK stop running.
Z = High impedance
X = Don’t care
2
PS8545 06/20/01