PI6CV855 Datasheet, PDF (1/9 Pages) Pericom Semiconductor Corporation – PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory

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PLL Clock Driver for 2.5V
SSTL 2 DDR SDRAM Memory
Product Features
• PLL clock distribution optimized for SSTL_2 DDR SDRAM
applications.
• Distributes one differential clock input pair to five differential
clock output pairs.
• Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2
• Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2
• External feedback pins (FBIN,FBIN) are used to
synchronize the outputs to the clock input.
• Operates at AV_DD = 2.5V for core circuit and internal PLL,
and V_DDQ = 2.5V for differential output drivers
• Available Package:
– Plastic 28-pin TSSOP
Product Description
PI6CV855 PLL clock device is developed for SSTL_DDR SDRAM
applications. This PLL Clock Buffer is designed for 2.5 V_DDQ and
2.5V AV_DD operation and differential data input and output levels.
The device is a zero delay buffer that distributes a differential clock
input pair (CLK, CLK) to five differential pairs of clock outputs
(Y[0:4], Y[0:4]) and one differential pair feedback clock outputs
(FBOUT, FBOUT). The clock outputs are controlled by the input
clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), and the
Analog Power input (AV_DD). When the AV_DD is strapped low, the
PLL is turned off and bypassed for test purposes.
When the input frequency falls below a suggested detection fre-
quency that is below the operating frequency of the PLL, the device
will enter a low power mode. In low power mode, PLL is turned OFF,
Y[0:4] and Y[0:4] outputs are 3-stated.
The PI6CV855 is able to track Spread Spectrum Clocking to reduce
EMI.
Block Diagram
CLK
CLK
FBIN
FBIN
AVDD
PLL
Logic
and
Test Ciruit
Pin Configuration
GND 1
28 Y4
Y0
Y0 2
27 Y4
Y0
Y0 3
26 VD _{D Q}
Y1
VD _{D Q 4}
25 GND
Y1
CLK 5
24 FBOUT
Y2
CLK 6 ^28-Pin 23 FBOUT
Y2
AVDD ₇
L ₂₂
VD _{D Q}
Y3
AGND 8
21 FBIN
Y3
GND 9
20 FBIN
Y4
Y1 10
19 GND
Y4
Y1 11
18 ^VD D Q
VD _{D Q 12}
17 Y3
Y2 13
16 Y3
Y2 14
15 GND
1
PS8545 06/20/01