PI2EQX3232B Datasheet, PDF (2/7 Pages) Pericom Semiconductor Corporation – 3.2Gbps, 2-Port, SATAi/m, Serial Re-Driver

Pin Description
Pin #
Pin Name
1
AI+
2
AI-
36
AO+
35
AO-
33
BI+
32
BI-
4
BO+
5
BO-
7
CI+
8
CI-
14
CKIN+
15
CKIN-
30
CO+
29
CO-
27
DI+
26
DI-
10
DO+
11
DO-
41, 40, 39, 38
EN_
[A,B,C,D]
13
EN_CLK
25, Center Pad
24
22
23
47
46
16
17
GND
IREF
OUT0+
OUT1-
SEL_EQ_A
SEL_EQ_B
SEL_EQ_C
SEL_EQ_D
07-0225
PI2EQX3232B
3.2Gbps, 2-Port, SATAi/m,
Serial Re-Driver
I/O
I
I
O
O
I
I
O
O
I
I
I
I
O
O
I
I
O
O
I
I
PWR
O
O
O
I
I
I
I
Description
Positive CML Input Channel A with internal 50Ω pull down
Negative CML Input Channel A with internal 50Ω pull down
Positive CML Output Channel A internal 50Ω pull up to VDD during normal opera-
tion and 2kΩ when EN_A=0. Drives to output common mode voltage when input is
<V_TH–.
Negative CML Output Channel A with internal 50Ω pull up to VDD during normal
operation and 2kΩ when EN_A=0. Drives to output common mode voltage when
input is <V_TH–.
Positive CML Input Channel B with internal 50Ω pull down
Negative CML Input Channel B with internal 50Ω pull down
Positive CML Output Channel B with internal 50Ω pull up to VDD during normal
operation and 2kΩ when EN_B=0. Drives to output common mode voltage when
input is <V_TH–.
Negative CML Output Channel B with internal 50Ω pull up to VDD during normal
operation and 2kΩ when EN_B=0. Drives to output common mode voltage when
input is <V_TH–.
Positive CML Input Channel C with internal 50Ω pull down
Negative CML Input Channel C with internal 50Ω pull down
Differential Input Reference Clock
Positive CML Output Channel C with internal 50Ω pull up to VDD during normal
operation and 2kΩ when EN_C=0. Drives to output common mode voltage when
input is <V_TH–.
Negative CML Output Channel C with internal 50Ω pull up to VDD during normal
operation and 2kΩ when EN_C=0. Drives to output common mode voltage when
input is <V_TH–.
Positive CML Input Channel D with internal 50Ω pull down
Negative CML Input Channel D with internal 50Ω pull down
Positive CML Output Channel D with internal 50Ω pull up to VDD during normal
operation and 2kΩ when EN_D=0. Drives to output common mode voltage when
input is <V_TH–.
Negative CML Output Channel C with internal 50Ω pull up to VDD during normal
operation and 2kΩ when EN_D=0. Drives to output common mode voltage when
input is <V_TH–.
Active HIGH LVCMOS signal input pins, when HIGH, it enables the CML output.
When LOW, it disables the CML output (x0+, x0-) to HI-z state. Both x0+ & x0- out-
puts will be pulled up to V_DD by internal 2kΩ resistor.
Active HIGH LVCMOS signal input pin. When HIGH, it enables the OUTx+/OUTx-
outputs. When LOW, it disables these outputs, with 50Ω to ground termination.
Supply Ground
External 475Ω resistor connection to set the differential output current
Differential Reference Clock Output
Selection pins for equalizer (see Amplifier Configuration Table)
w/ 50kΩ internal pull up
2
PS8889D
10/03/07