PI2EQX3232B Datasheet, PDF (1/7 Pages) Pericom Semiconductor Corporation – 3.2Gbps, 2-Port, SATAi/m, Serial Re-Driver

PI2EQX3232B
3.2Gbps, 2-Port, SATAi/m, Serial Re-Driver
Features
• Supports data rates up to 3.2Gbps on each lane
• Adjustable Transmiter De-Emphasis & Amplitude
• Adjustable Receiver Equalization
• Spectrum Reference Clock Buffer Output
• Optimized for SATAi/m applications
• Input signal level detection & output squelch on all channels
• 100-Ohm Differential CML I/O’s
• Low Power (100mW per Channel)
• Standby Mode – Power Down State
• V_DD Operating Range: 1.8V +/-0.1V
• Packaging (Pb-free & Green):48-contact TQFN
Block Diagram
Description
Pericom Semiconductor’s PI2EQX3232B is a low power, signal
Re-Driver. The device provides programmable equalization,
amplification, and de-emphasis, to optimize performance over a
variety of physical mediums by reducing Inter-Symbol Interference
(ISI). PI2EQX3232B supports four 100-Ohm Differential CML
data I/O’s between the Protocol ASIC to a switch fabric, across
a backplane, or to extend the signals across other distant data
pathways on the user’s platform.
The integrated equalization circuitry provides flexibility with
signal integrity of the signal before the Re-Driver. Whereas the
integrated de-emphasis circuitry provides flexibility with signal
integrity of the signal after the Re-Driver.
A low-level input signal detection and output squelch function
is provided for all four channels. Each channel operates fully
independantly. When a channel is enabled (EN_x=1) and
operating, that channels input signal level (on xI+/-) determines
whether the output is enabled. If the input level of the channel
falls below the active threshold level (Vth-) then the output driver
switches off, and the pin is pulled to VDD via a high impedance
resistor. If the input level of the channel falls below the active
threshold level (Vth-) then the outputs are driven to the common
mode voltage.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX3232B also provides power management Stand-by mode
operated by an Enable pin.
Pin Description
Signal Detect
CML
xI+
xI-
SEL_EQ _x
EN_x
CKIN-
CKIN+
Equalizer
Limiting
Amp
CML
xO+
xO-
Power
Management
SEL_OL_x SEL_DE_ x
-- Repeated 4 times --
Buffer
IREF
EN_
OUT-
CLK
OUT+
AI+ 1
AI- ²
VDD ³
BO+ ⁴
BO- 5
VDD 6
CI+ ⁷
CI- 8
VDD ⁹
DO+ 10
DO- 11
VDD 12
GND
36 AO+
35 AO-
34 VDD
33 BI+
32 BI-
31 VDD
30 CO+
29 CO-
28 VDD
27 DI+
26 DI-
25 GND
07-0225
1
PS8889D
10/03/07