PT7C4337A Datasheet, PDF (18/25 Pages) Pericom Semiconductor Corporation – Real-time Clock Module

PT7C4337A/4337AC
Real-time Clock Module (I²C Bus)
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SCL from Master
1
2
8
9
SDA from transmitter
(sending side)
Release SDA
SDA from receiver
(receiving side)
Low active
ACK signal
After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the
falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the
transmitter.
When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave, that
indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits a
STOP condition from the Master.
Slave Address
The I²C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin,
slave addresses are allocated to each device.
All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving device
responds to this communication only when the specified slave address it has received matches its own slave address.
Slave addresses have a fixed length of 7 bits. See table for the details.
An R/W bit is added to each 7-bit slave address during 8-bit transfers.
Table
Operation
Slave address
Transfer data
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1
R / W bit
bit 0
Read
Write
D1 h
D0 h
1
1
0
1
0
0
0
1 (= Read)
0 (= Write)
I²C Bus’s Basic Transfer Format
S Start indication
P Stop indication
A RTC Acknowledge
Sr Restart indication
A Master Acknowledge
2014-10-0002
PT0480-2 11/03/14
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