PI6C105 Datasheet, PDF (11/15 Pages) Pericom Semiconductor Corporation – Precision Clock Synthesizer for Mobile PCs

PI6C105
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AC Timing
Figure 1. Host Clock
to PCI CLK Offset
Parameters
t_HKP (2.5V)
t_HKH (2.5V)
t_HKL (2.5V)
t_HRISE (2.5V)
t_HFALL (2.5V)
t_JITTER (2.5V)
Duty Cycle (2.5V)
t_HSKW (2.5V)
t_PZL, t_PZH
t_PLZ, t_PHZ
t_HSTB
t_PKP
t_PKPS
tPKH
t_PKL
t_PSKW
t_HPOFFSET
t_PSTB
Host CLK period
Host CLK high time
Host CLK low time
Host CLK rise time
Host CLK fall time
Host CLK Jitter
Measured at 1.25V
Host Bus CLK Skew
Output enable delay
Output disable delay
Host CLK Stabilization from power-up
PCI CLK period
PCI CLK period stability
PCI CLK high time
PCI CLK low time
PCI Bus CLK Skew
Host to PCI Clock Offset
PCI CLK Stabilization from power-up
66 MHz
Min. Max.
15.0
15.5
5.2
5.0
0.4
1.6
0.4
1.6
250
45
55
175
1.0
8.0
1.0
8.0
3
30.0
µ
500
12.0
12.0
500
1.5
4.0
3
100 MHz
Min. Max.
10.0 10.5
3.0
2.8
0.4
1.6
0.4
1.6
250
45
55
175
1.0
8.0
1.0
8.0
3
30.0
µ
500
12.0
12.0
500
1.5
4.0
3
Units
ns
ps
%
ps
ns
ms
ns
ps
ns
ps
ns
ms
258
PS8316 03/15/99